Trong Q Phan

Array ( [id] => 4252639 [patent_doc_number] => 06166992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/517338 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 66 [patent_no_of_words] => 24410 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166992.pdf [firstpage_image] =>[orig_patent_app_number] => 517338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1219947 [patent_doc_number] => 06707713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Interlaced multi-level memory' [patent_app_type] => B1 [patent_app_number] => 09/516478 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2311 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707713.pdf [firstpage_image] =>[orig_patent_app_number] => 09516478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4383897 [patent_doc_number] => 06288924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device and process for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/512479 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 8715 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288924.pdf [firstpage_image] =>[orig_patent_app_number] => 512479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363351 [patent_doc_number] => 06215687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor device and process for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/512476 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 8713 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215687.pdf [firstpage_image] =>[orig_patent_app_number] => 512476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417233 [patent_doc_number] => 06172894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Semiconductor memory cell having more than two stable states' [patent_app_type] => 1 [patent_app_number] => 9/505082 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172894.pdf [firstpage_image] =>[orig_patent_app_number] => 505082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4418557 [patent_doc_number] => 06240001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'CAM match line precharge' [patent_app_type] => 1 [patent_app_number] => 9/496994 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1668 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240001.pdf [firstpage_image] =>[orig_patent_app_number] => 496994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202574 [patent_doc_number] => 06154418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Write scheme for a double data rate SDRAM' [patent_app_type] => 1 [patent_app_number] => 9/503212 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5187 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154418.pdf [firstpage_image] =>[orig_patent_app_number] => 503212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363864 [patent_doc_number] => 06215721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Multi-bank memory device and method for arranging input/output lines' [patent_app_type] => 1 [patent_app_number] => 9/499576 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4763 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215721.pdf [firstpage_image] =>[orig_patent_app_number] => 499576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417584 [patent_doc_number] => 06172924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Memory device with a sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/497295 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2817 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172924.pdf [firstpage_image] =>[orig_patent_app_number] => 497295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1319133 [patent_doc_number] => 06614684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Semiconductor integrated circuit and nonvolatile memory element' [patent_app_type] => B1 [patent_app_number] => 09/493280 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 22371 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614684.pdf [firstpage_image] =>[orig_patent_app_number] => 09493280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4369262 [patent_doc_number] => 06219271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/490080 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4272 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219271.pdf [firstpage_image] =>[orig_patent_app_number] => 490080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4251960 [patent_doc_number] => 06166946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'System and method for writing to and reading from a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/489380 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6263 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166946.pdf [firstpage_image] =>[orig_patent_app_number] => 489380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4284880 [patent_doc_number] => 06246616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Memory device having redundancy cells' [patent_app_type] => 1 [patent_app_number] => 9/487878 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7611 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246616.pdf [firstpage_image] =>[orig_patent_app_number] => 487878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4273361 [patent_doc_number] => 06259635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 9/491476 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4476 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259635.pdf [firstpage_image] =>[orig_patent_app_number] => 491476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4308871 [patent_doc_number] => 06181592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/484276 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4406 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181592.pdf [firstpage_image] =>[orig_patent_app_number] => 484276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305153 [patent_doc_number] => 06236601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor memory device having faulty cells' [patent_app_type] => 1 [patent_app_number] => 9/477665 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12494 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236601.pdf [firstpage_image] =>[orig_patent_app_number] => 477665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407011 [patent_doc_number] => 06297984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Structure and method for protecting integrated circuits during plasma processing' [patent_app_type] => 1 [patent_app_number] => 9/474376 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4456 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297984.pdf [firstpage_image] =>[orig_patent_app_number] => 474376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1488536 [patent_doc_number] => 06366487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Plurality of integrated circuit chips' [patent_app_type] => B1 [patent_app_number] => 09/474880 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3667 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366487.pdf [firstpage_image] =>[orig_patent_app_number] => 09474880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261970 [patent_doc_number] => 06137743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor memory device with reduced consumption of standby current in refresh mode' [patent_app_type] => 1 [patent_app_number] => 9/472982 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4144 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137743.pdf [firstpage_image] =>[orig_patent_app_number] => 472982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309349 [patent_doc_number] => 06181623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor MOS/BIPOLAR composite transistor and semiconductor memory device using the same' [patent_app_type] => 1 [patent_app_number] => 9/472984 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4312 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181623.pdf [firstpage_image] =>[orig_patent_app_number] => 472984 [rel_patent_id] =>[rel_patent_doc_number] =>)