Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4261527 [patent_doc_number] => 06137713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 9/420576 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6448 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137713.pdf [firstpage_image] =>[orig_patent_app_number] => 420576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420576
Semiconductor storage device Oct 18, 1999 Issued
Array ( [id] => 4309625 [patent_doc_number] => 06185128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Reference cell four-way switch for a simultaneous operation flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/421984 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8004 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185128.pdf [firstpage_image] =>[orig_patent_app_number] => 421984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421984
Reference cell four-way switch for a simultaneous operation flash memory device Oct 18, 1999 Issued
Array ( [id] => 4229752 [patent_doc_number] => 06111787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Address transistion detect timing architecture for a simultaneous operation flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/421776 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 13 [patent_no_of_words] => 13625 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111787.pdf [firstpage_image] =>[orig_patent_app_number] => 421776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421776
Address transistion detect timing architecture for a simultaneous operation flash memory device Oct 18, 1999 Issued
Array ( [id] => 4165688 [patent_doc_number] => 06125058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/421982 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9288 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125058.pdf [firstpage_image] =>[orig_patent_app_number] => 421982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421982
System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device Oct 18, 1999 Issued
Array ( [id] => 4252426 [patent_doc_number] => 06166976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Multiple equilibration circuits for a single bit line' [patent_app_type] => 1 [patent_app_number] => 9/418959 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 3 [patent_no_of_words] => 3135 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166976.pdf [firstpage_image] =>[orig_patent_app_number] => 418959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418959
Multiple equilibration circuits for a single bit line Oct 14, 1999 Issued
Array ( [id] => 4302878 [patent_doc_number] => 06212128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Address transition detector in semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 9/413382 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3985 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212128.pdf [firstpage_image] =>[orig_patent_app_number] => 413382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413382
Address transition detector in semiconductor memories Oct 5, 1999 Issued
Array ( [id] => 4147816 [patent_doc_number] => 06122198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Bit by bit APDE verify for flash memory applications' [patent_app_type] => 1 [patent_app_number] => 9/413182 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5087 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122198.pdf [firstpage_image] =>[orig_patent_app_number] => 413182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413182
Bit by bit APDE verify for flash memory applications Oct 4, 1999 Issued
Array ( [id] => 4301009 [patent_doc_number] => 06184554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Memory cell with self-aligned floating gate and separate select gate, and fabrication process' [patent_app_type] => 1 [patent_app_number] => 9/412854 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 5412 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184554.pdf [firstpage_image] =>[orig_patent_app_number] => 412854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412854
Memory cell with self-aligned floating gate and separate select gate, and fabrication process Oct 4, 1999 Issued
Array ( [id] => 4202542 [patent_doc_number] => 06154416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Column address decoder for two bit prefetch of semiconductor memory device and decoding method thereof' [patent_app_type] => 1 [patent_app_number] => 9/409178 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5534 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154416.pdf [firstpage_image] =>[orig_patent_app_number] => 409178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409178
Column address decoder for two bit prefetch of semiconductor memory device and decoding method thereof Sep 29, 1999 Issued
Array ( [id] => 4229924 [patent_doc_number] => 06111799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Semiconductor memory in which access to broken word line is inhibited' [patent_app_type] => 1 [patent_app_number] => 9/408180 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5495 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111799.pdf [firstpage_image] =>[orig_patent_app_number] => 408180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408180
Semiconductor memory in which access to broken word line is inhibited Sep 28, 1999 Issued
Array ( [id] => 4153151 [patent_doc_number] => 06061289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Variable potential generating circuit using current-scaling adding type D/A converter circuit in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/406731 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 12177 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061289.pdf [firstpage_image] =>[orig_patent_app_number] => 406731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406731
Variable potential generating circuit using current-scaling adding type D/A converter circuit in semiconductor memory device Sep 27, 1999 Issued
Array ( [id] => 4231675 [patent_doc_number] => 06088288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Memory device and method of reducing ground bounce in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/405480 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4069 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088288.pdf [firstpage_image] =>[orig_patent_app_number] => 405480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405480
Memory device and method of reducing ground bounce in a memory device Sep 23, 1999 Issued
Array ( [id] => 4423847 [patent_doc_number] => 06311312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method for modeling a conductive semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/405510 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3046 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311312.pdf [firstpage_image] =>[orig_patent_app_number] => 405510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405510
Method for modeling a conductive semiconductor substrate Sep 22, 1999 Issued
Array ( [id] => 4417487 [patent_doc_number] => 06172914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Concurrent erase verify scheme for flash memory applications' [patent_app_type] => 1 [patent_app_number] => 9/404078 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4439 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172914.pdf [firstpage_image] =>[orig_patent_app_number] => 404078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404078
Concurrent erase verify scheme for flash memory applications Sep 22, 1999 Issued
Array ( [id] => 4108737 [patent_doc_number] => 06049479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell' [patent_app_type] => 1 [patent_app_number] => 9/404080 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3818 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049479.pdf [firstpage_image] =>[orig_patent_app_number] => 404080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404080
Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell Sep 22, 1999 Issued
Array ( [id] => 4261468 [patent_doc_number] => 06137710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Connecting apparatus, and information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/395766 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10275 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137710.pdf [firstpage_image] =>[orig_patent_app_number] => 395766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395766
Connecting apparatus, and information processing apparatus Sep 13, 1999 Issued
Array ( [id] => 4136768 [patent_doc_number] => 06034387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Methods of operating ferroelectric memory devices having linear reference cells therein' [patent_app_type] => 1 [patent_app_number] => 9/395544 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4107 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034387.pdf [firstpage_image] =>[orig_patent_app_number] => 395544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395544
Methods of operating ferroelectric memory devices having linear reference cells therein Sep 13, 1999 Issued
Array ( [id] => 4218895 [patent_doc_number] => 06040218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Two square NVRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/394093 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 3056 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040218.pdf [firstpage_image] =>[orig_patent_app_number] => 394093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394093
Two square NVRAM cell Sep 12, 1999 Issued
Array ( [id] => 4387552 [patent_doc_number] => 06304104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method and apparatus for reducing worst case power' [patent_app_type] => 1 [patent_app_number] => 9/394984 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 7806 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304104.pdf [firstpage_image] =>[orig_patent_app_number] => 394984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394984
Method and apparatus for reducing worst case power Sep 12, 1999 Issued
Array ( [id] => 4399927 [patent_doc_number] => 06295631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method for determining the compensation value of the width of a wire by measuring the resistance of the wire' [patent_app_type] => 1 [patent_app_number] => 9/395681 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1591 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295631.pdf [firstpage_image] =>[orig_patent_app_number] => 395681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395681
Method for determining the compensation value of the width of a wire by measuring the resistance of the wire Sep 12, 1999 Issued
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