
Trong Q Phan
Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2827, 2511, 2504, 2824, 2825, 2899, 2818 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4265753
[patent_doc_number] => 06208544
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Content addressable memory cell providing simultaneous read and compare capability'
[patent_app_type] => 1
[patent_app_number] => 9/391918
[patent_app_country] => US
[patent_app_date] => 1999-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2773
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/208/06208544.pdf
[firstpage_image] =>[orig_patent_app_number] => 391918
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/391918 | Content addressable memory cell providing simultaneous read and compare capability | Sep 8, 1999 | Issued |
Array
(
[id] => 4262845
[patent_doc_number] => 06222774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Data-erasable non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/391180
[patent_app_country] => US
[patent_app_date] => 1999-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 11130
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/222/06222774.pdf
[firstpage_image] =>[orig_patent_app_number] => 391180
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/391180 | Data-erasable non-volatile semiconductor memory device | Sep 7, 1999 | Issued |
Array
(
[id] => 4110270
[patent_doc_number] => 06097636
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Word line and source line driver circuitries'
[patent_app_type] => 1
[patent_app_number] => 9/390060
[patent_app_country] => US
[patent_app_date] => 1999-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3214
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/097/06097636.pdf
[firstpage_image] =>[orig_patent_app_number] => 390060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/390060 | Word line and source line driver circuitries | Sep 2, 1999 | Issued |
Array
(
[id] => 4185631
[patent_doc_number] => 06141276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Apparatus and method for increasing test flexibility of a memory device'
[patent_app_type] => 1
[patent_app_number] => 9/389680
[patent_app_country] => US
[patent_app_date] => 1999-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5170
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141276.pdf
[firstpage_image] =>[orig_patent_app_number] => 389680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389680 | Apparatus and method for increasing test flexibility of a memory device | Sep 1, 1999 | Issued |
Array
(
[id] => 4401209
[patent_doc_number] => 06305004
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-16
[patent_title] => 'Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing'
[patent_app_type] => 1
[patent_app_number] => 9/387062
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 5267
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/305/06305004.pdf
[firstpage_image] =>[orig_patent_app_number] => 387062
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387062 | Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing | Aug 30, 1999 | Issued |
Array
(
[id] => 4229979
[patent_doc_number] => 06111803
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Reduced cell voltage for memory device'
[patent_app_type] => 1
[patent_app_number] => 9/385478
[patent_app_country] => US
[patent_app_date] => 1999-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6955
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/111/06111803.pdf
[firstpage_image] =>[orig_patent_app_number] => 385478
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/385478 | Reduced cell voltage for memory device | Aug 29, 1999 | Issued |
Array
(
[id] => 4185055
[patent_doc_number] => 06141238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same'
[patent_app_type] => 1
[patent_app_number] => 9/385380
[patent_app_country] => US
[patent_app_date] => 1999-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 33
[patent_no_of_words] => 10178
[patent_no_of_claims] => 61
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141238.pdf
[firstpage_image] =>[orig_patent_app_number] => 385380
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/385380 | Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same | Aug 29, 1999 | Issued |
Array
(
[id] => 4229768
[patent_doc_number] => 06111788
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Method for programming and erasing a triple-poly split-gate flash'
[patent_app_type] => 1
[patent_app_number] => 9/382078
[patent_app_country] => US
[patent_app_date] => 1999-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3499
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/111/06111788.pdf
[firstpage_image] =>[orig_patent_app_number] => 382078
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/382078 | Method for programming and erasing a triple-poly split-gate flash | Aug 23, 1999 | Issued |
Array
(
[id] => 4412951
[patent_doc_number] => 06298471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Interconnect minimization in processor design'
[patent_app_type] => 1
[patent_app_number] => 9/378295
[patent_app_country] => US
[patent_app_date] => 1999-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 26
[patent_no_of_words] => 8470
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/298/06298471.pdf
[firstpage_image] =>[orig_patent_app_number] => 378295
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/378295 | Interconnect minimization in processor design | Aug 19, 1999 | Issued |
Array
(
[id] => 4425567
[patent_doc_number] => 06178123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Semiconductor device with circuit for phasing internal clock signal'
[patent_app_type] => 1
[patent_app_number] => 9/377904
[patent_app_country] => US
[patent_app_date] => 1999-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 8126
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/178/06178123.pdf
[firstpage_image] =>[orig_patent_app_number] => 377904
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/377904 | Semiconductor device with circuit for phasing internal clock signal | Aug 19, 1999 | Issued |
Array
(
[id] => 4095789
[patent_doc_number] => 06163482
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'One transistor EEPROM cell using ferro-electric spacer'
[patent_app_type] => 1
[patent_app_number] => 9/378558
[patent_app_country] => US
[patent_app_date] => 1999-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2199
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163482.pdf
[firstpage_image] =>[orig_patent_app_number] => 378558
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/378558 | One transistor EEPROM cell using ferro-electric spacer | Aug 18, 1999 | Issued |
Array
(
[id] => 1454400
[patent_doc_number] => 06456543
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Data input/output circuit for semiconductor memory device'
[patent_app_type] => B1
[patent_app_number] => 09/376016
[patent_app_country] => US
[patent_app_date] => 1999-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 3468
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/456/06456543.pdf
[firstpage_image] =>[orig_patent_app_number] => 09376016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376016 | Data input/output circuit for semiconductor memory device | Aug 17, 1999 | Issued |
Array
(
[id] => 4251950
[patent_doc_number] => 06091653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Method of sensing data in semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/375448
[patent_app_country] => US
[patent_app_date] => 1999-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2267
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/091/06091653.pdf
[firstpage_image] =>[orig_patent_app_number] => 375448
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375448 | Method of sensing data in semiconductor memory device | Aug 16, 1999 | Issued |
Array
(
[id] => 4272821
[patent_doc_number] => 06205064
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Semiconductor memory device having program circuit'
[patent_app_type] => 1
[patent_app_number] => 9/376060
[patent_app_country] => US
[patent_app_date] => 1999-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 20015
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/205/06205064.pdf
[firstpage_image] =>[orig_patent_app_number] => 376060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376060 | Semiconductor memory device having program circuit | Aug 16, 1999 | Issued |
Array
(
[id] => 4155360
[patent_doc_number] => 06031776
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Sense amplifier circuit for a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/376750
[patent_app_country] => US
[patent_app_date] => 1999-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1440
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/031/06031776.pdf
[firstpage_image] =>[orig_patent_app_number] => 376750
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376750 | Sense amplifier circuit for a semiconductor memory device | Aug 16, 1999 | Issued |
Array
(
[id] => 4216653
[patent_doc_number] => 06078513
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'NMOS dynamic content-addressable-memory CAM cell with self-booting pass transistors and local row and column select'
[patent_app_type] => 1
[patent_app_number] => 9/375979
[patent_app_country] => US
[patent_app_date] => 1999-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6297
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078513.pdf
[firstpage_image] =>[orig_patent_app_number] => 375979
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375979 | NMOS dynamic content-addressable-memory CAM cell with self-booting pass transistors and local row and column select | Aug 15, 1999 | Issued |
Array
(
[id] => 4159574
[patent_doc_number] => 06064609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Semiconductor memory device with true/complement redundancy scheme'
[patent_app_type] => 1
[patent_app_number] => 9/373447
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7600
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/064/06064609.pdf
[firstpage_image] =>[orig_patent_app_number] => 373447
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373447 | Semiconductor memory device with true/complement redundancy scheme | Aug 11, 1999 | Issued |
Array
(
[id] => 4359235
[patent_doc_number] => 06285621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Method of minimizing the access time in semiconductor memories'
[patent_app_type] => 1
[patent_app_number] => 9/373476
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2257
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/285/06285621.pdf
[firstpage_image] =>[orig_patent_app_number] => 373476
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373476 | Method of minimizing the access time in semiconductor memories | Aug 11, 1999 | Issued |
Array
(
[id] => 798589
[patent_doc_number] => 07428182
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-09-23
[patent_title] => 'Electronic circuit system, and signal transmission method, to improve signal transmission efficiency and simplify signal transmission management'
[patent_app_type] => utility
[patent_app_number] => 09/372166
[patent_app_country] => US
[patent_app_date] => 1999-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6811
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/428/07428182.pdf
[firstpage_image] =>[orig_patent_app_number] => 09372166
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/372166 | Electronic circuit system, and signal transmission method, to improve signal transmission efficiency and simplify signal transmission management | Aug 10, 1999 | Issued |
Array
(
[id] => 4305110
[patent_doc_number] => 06236598
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Clamping circuit for cell plate in DRAM'
[patent_app_type] => 1
[patent_app_number] => 9/372076
[patent_app_country] => US
[patent_app_date] => 1999-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5570
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/236/06236598.pdf
[firstpage_image] =>[orig_patent_app_number] => 372076
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/372076 | Clamping circuit for cell plate in DRAM | Aug 10, 1999 | Issued |