Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4165408 [patent_doc_number] => 06157243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Device and method for generating a high voltage' [patent_app_type] => 1 [patent_app_number] => 9/371549 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3494 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157243.pdf [firstpage_image] =>[orig_patent_app_number] => 371549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371549
Device and method for generating a high voltage Aug 9, 1999 Issued
Array ( [id] => 4254450 [patent_doc_number] => 06222227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Memory cell with self-aligned floating gate and separate select gate, and fabrication process' [patent_app_type] => 1 [patent_app_number] => 9/370557 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4762 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222227.pdf [firstpage_image] =>[orig_patent_app_number] => 370557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370557
Memory cell with self-aligned floating gate and separate select gate, and fabrication process Aug 8, 1999 Issued
Array ( [id] => 4102516 [patent_doc_number] => 06134138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and apparatus for reading a magnetoresistive memory' [patent_app_type] => 1 [patent_app_number] => 9/365308 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134138.pdf [firstpage_image] =>[orig_patent_app_number] => 365308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365308
Method and apparatus for reading a magnetoresistive memory Jul 29, 1999 Issued
Array ( [id] => 4366895 [patent_doc_number] => 06191613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Programmable logic device with delay-locked loop' [patent_app_type] => 1 [patent_app_number] => 9/363941 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3589 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191613.pdf [firstpage_image] =>[orig_patent_app_number] => 363941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363941
Programmable logic device with delay-locked loop Jul 28, 1999 Issued
Array ( [id] => 4420090 [patent_doc_number] => 06229746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Pulse generator circuitry for timing a low-power memory device' [patent_app_type] => 1 [patent_app_number] => 9/363797 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2672 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229746.pdf [firstpage_image] =>[orig_patent_app_number] => 363797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363797
Pulse generator circuitry for timing a low-power memory device Jul 28, 1999 Issued
Array ( [id] => 4197378 [patent_doc_number] => 06094393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Stacked sense-amp cache memory system and method' [patent_app_type] => 1 [patent_app_number] => 9/363517 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4705 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094393.pdf [firstpage_image] =>[orig_patent_app_number] => 363517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363517
Stacked sense-amp cache memory system and method Jul 28, 1999 Issued
Array ( [id] => 1425586 [patent_doc_number] => 06507211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Programmable logic device capable of preserving user data during partial or complete reconfiguration' [patent_app_type] => B1 [patent_app_number] => 09/363990 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507211.pdf [firstpage_image] =>[orig_patent_app_number] => 09363990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363990
Programmable logic device capable of preserving user data during partial or complete reconfiguration Jul 28, 1999 Issued
Array ( [id] => 1472179 [patent_doc_number] => 06407580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Latch sense amplifier circuit with an improved next stage buffer' [patent_app_type] => B1 [patent_app_number] => 09/362026 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8283 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407580.pdf [firstpage_image] =>[orig_patent_app_number] => 09362026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362026
Latch sense amplifier circuit with an improved next stage buffer Jul 27, 1999 Issued
Array ( [id] => 4399912 [patent_doc_number] => 06295630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method and apparatus for measuring an overlap length of MISFET, and a recording medium and a device model each carrying an extraction program for determining the overlap length' [patent_app_type] => 1 [patent_app_number] => 9/362101 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 14263 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295630.pdf [firstpage_image] =>[orig_patent_app_number] => 362101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362101
Method and apparatus for measuring an overlap length of MISFET, and a recording medium and a device model each carrying an extraction program for determining the overlap length Jul 27, 1999 Issued
Array ( [id] => 4243714 [patent_doc_number] => 06091095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Semiconductor storage' [patent_app_type] => 1 [patent_app_number] => 9/362550 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5339 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091095.pdf [firstpage_image] =>[orig_patent_app_number] => 362550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362550
Semiconductor storage Jul 27, 1999 Issued
Array ( [id] => 4302423 [patent_doc_number] => 06181160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Programmable logic device with hierarchical interconnection resources' [patent_app_type] => 1 [patent_app_number] => 9/363162 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8009 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181160.pdf [firstpage_image] =>[orig_patent_app_number] => 363162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363162
Programmable logic device with hierarchical interconnection resources Jul 27, 1999 Issued
Array ( [id] => 4280284 [patent_doc_number] => 06323685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Threshold voltage scalable buffer with reference level' [patent_app_type] => 1 [patent_app_number] => 9/361455 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4310 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323685.pdf [firstpage_image] =>[orig_patent_app_number] => 361455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361455
Threshold voltage scalable buffer with reference level Jul 26, 1999 Issued
Array ( [id] => 7639613 [patent_doc_number] => 06396303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Expandable interconnect structure for FPGAS' [patent_app_type] => B1 [patent_app_number] => 09/361790 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 21278 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396303.pdf [firstpage_image] =>[orig_patent_app_number] => 09361790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361790
Expandable interconnect structure for FPGAS Jul 26, 1999 Issued
Array ( [id] => 6094342 [patent_doc_number] => 20020051391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'INTEGRATED CIRCUIT HAVING FORCED SUBSTRATE TEST MODE WITH IMPROVED SUBSTRATE ISOLATION' [patent_app_type] => new [patent_app_number] => 09/361009 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3801 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051391.pdf [firstpage_image] =>[orig_patent_app_number] => 09361009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361009
Integrated circuit having forced substrate test mode with improved substrate isolation Jul 26, 1999 Issued
Array ( [id] => 4250696 [patent_doc_number] => 06144603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/359914 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3710 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144603.pdf [firstpage_image] =>[orig_patent_app_number] => 359914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359914
Semiconductor memory device Jul 25, 1999 Issued
Array ( [id] => 4267963 [patent_doc_number] => 06259277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Use of molecular electrostatic potential to process electronic signals' [patent_app_type] => 1 [patent_app_number] => 9/360814 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6529 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259277.pdf [firstpage_image] =>[orig_patent_app_number] => 360814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360814
Use of molecular electrostatic potential to process electronic signals Jul 25, 1999 Issued
Array ( [id] => 4250626 [patent_doc_number] => 06081461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Circuit and method for a memory device with p-channel isolation gates' [patent_app_type] => 1 [patent_app_number] => 9/361103 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4414 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081461.pdf [firstpage_image] =>[orig_patent_app_number] => 361103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361103
Circuit and method for a memory device with p-channel isolation gates Jul 25, 1999 Issued
Array ( [id] => 4413208 [patent_doc_number] => 06172518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of minimizing power use in programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 9/360111 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6728 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172518.pdf [firstpage_image] =>[orig_patent_app_number] => 360111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360111
Method of minimizing power use in programmable logic devices Jul 22, 1999 Issued
Array ( [id] => 4426439 [patent_doc_number] => 06226222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Synchronous semiconductor memory device having a function for controlling sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 9/359217 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2794 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226222.pdf [firstpage_image] =>[orig_patent_app_number] => 359217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359217
Synchronous semiconductor memory device having a function for controlling sense amplifiers Jul 21, 1999 Issued
Array ( [id] => 4191644 [patent_doc_number] => 06150847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Device and method for generating a variable duty cycle clock' [patent_app_type] => 1 [patent_app_number] => 9/358013 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3436 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150847.pdf [firstpage_image] =>[orig_patent_app_number] => 358013 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358013
Device and method for generating a variable duty cycle clock Jul 20, 1999 Issued
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