
Trong Q Phan
Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2827, 2511, 2504, 2824, 2825, 2899, 2818 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4412660
[patent_doc_number] => 06232796
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Apparatus and method for detecting two data bits per clock edge'
[patent_app_type] => 1
[patent_app_number] => 9/358054
[patent_app_country] => US
[patent_app_date] => 1999-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 3989
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/232/06232796.pdf
[firstpage_image] =>[orig_patent_app_number] => 358054
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/358054 | Apparatus and method for detecting two data bits per clock edge | Jul 20, 1999 | Issued |
Array
(
[id] => 6138594
[patent_doc_number] => 20020000834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'SEMICONDUCTOR LOGIC CIRCUIT DEVICE OF LOW CURRENT CONSUMPTION'
[patent_app_type] => new
[patent_app_number] => 09/356351
[patent_app_country] => US
[patent_app_date] => 1999-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 18991
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20020000834.pdf
[firstpage_image] =>[orig_patent_app_number] => 09356351
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/356351 | Semiconductor logic circuit device of low current consumption | Jul 18, 1999 | Issued |
Array
(
[id] => 4250668
[patent_doc_number] => 06144601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Semiconductor memory having an improved reading circuit'
[patent_app_type] => 1
[patent_app_number] => 9/354599
[patent_app_country] => US
[patent_app_date] => 1999-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9387
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144601.pdf
[firstpage_image] =>[orig_patent_app_number] => 354599
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354599 | Semiconductor memory having an improved reading circuit | Jul 15, 1999 | Issued |
Array
(
[id] => 1361968
[patent_doc_number] => 06587968
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'CAN bus termination circuits and CAN bus auto-termination methods'
[patent_app_type] => B1
[patent_app_number] => 09/354878
[patent_app_country] => US
[patent_app_date] => 1999-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 3635
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/587/06587968.pdf
[firstpage_image] =>[orig_patent_app_number] => 09354878
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354878 | CAN bus termination circuits and CAN bus auto-termination methods | Jul 15, 1999 | Issued |
Array
(
[id] => 4388952
[patent_doc_number] => 06294926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Very fine-grain field programmable gate array architecture and circuitry'
[patent_app_type] => 1
[patent_app_number] => 9/354607
[patent_app_country] => US
[patent_app_date] => 1999-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 5546
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294926.pdf
[firstpage_image] =>[orig_patent_app_number] => 354607
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/354607 | Very fine-grain field programmable gate array architecture and circuitry | Jul 15, 1999 | Issued |
Array
(
[id] => 4185467
[patent_doc_number] => 06141265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Clock synchronous memory'
[patent_app_type] => 1
[patent_app_number] => 9/353799
[patent_app_country] => US
[patent_app_date] => 1999-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3679
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141265.pdf
[firstpage_image] =>[orig_patent_app_number] => 353799
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353799 | Clock synchronous memory | Jul 14, 1999 | Issued |
Array
(
[id] => 4250727
[patent_doc_number] => 06081468
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/353856
[patent_app_country] => US
[patent_app_date] => 1999-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 8706
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/081/06081468.pdf
[firstpage_image] =>[orig_patent_app_number] => 353856
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353856 | Semiconductor device | Jul 14, 1999 | Issued |
Array
(
[id] => 1190292
[patent_doc_number] => 06734699
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-11
[patent_title] => 'Self-clocked complementary logic'
[patent_app_type] => B1
[patent_app_number] => 09/353726
[patent_app_country] => US
[patent_app_date] => 1999-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3071
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/734/06734699.pdf
[firstpage_image] =>[orig_patent_app_number] => 09353726
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353726 | Self-clocked complementary logic | Jul 13, 1999 | Issued |
Array
(
[id] => 4425557
[patent_doc_number] => 06195286
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Circuit and method for reading a non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 9/353756
[patent_app_country] => US
[patent_app_date] => 1999-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2914
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/195/06195286.pdf
[firstpage_image] =>[orig_patent_app_number] => 353756
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353756 | Circuit and method for reading a non-volatile memory | Jul 13, 1999 | Issued |
| 09/352717 | SEMICONDUCTOR MEMORY | Jul 12, 1999 | Abandoned |
Array
(
[id] => 4367905
[patent_doc_number] => 06201738
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'Nonvolatile semiconductor memory and program verification method in which number of write operation can be reduced in program verification operation'
[patent_app_type] => 1
[patent_app_number] => 9/352397
[patent_app_country] => US
[patent_app_date] => 1999-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 9111
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/201/06201738.pdf
[firstpage_image] =>[orig_patent_app_number] => 352397
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/352397 | Nonvolatile semiconductor memory and program verification method in which number of write operation can be reduced in program verification operation | Jul 12, 1999 | Issued |
Array
(
[id] => 4424415
[patent_doc_number] => 06301690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-09
[patent_title] => 'Method to improve integrated circuit defect limited yield'
[patent_app_type] => 1
[patent_app_number] => 9/294495
[patent_app_country] => US
[patent_app_date] => 1999-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2933
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/301/06301690.pdf
[firstpage_image] =>[orig_patent_app_number] => 294495
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/294495 | Method to improve integrated circuit defect limited yield | Jul 11, 1999 | Issued |
Array
(
[id] => 4415889
[patent_doc_number] => 06229340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/351321
[patent_app_country] => US
[patent_app_date] => 1999-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2270
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/229/06229340.pdf
[firstpage_image] =>[orig_patent_app_number] => 351321
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351321 | Semiconductor integrated circuit | Jul 11, 1999 | Issued |
Array
(
[id] => 4197672
[patent_doc_number] => 06130548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Signal converting receiver having constant hysteresis, and method therefor'
[patent_app_type] => 1
[patent_app_number] => 9/350642
[patent_app_country] => US
[patent_app_date] => 1999-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5567
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/130/06130548.pdf
[firstpage_image] =>[orig_patent_app_number] => 350642
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350642 | Signal converting receiver having constant hysteresis, and method therefor | Jul 8, 1999 | Issued |
Array
(
[id] => 4413188
[patent_doc_number] => 06172516
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Output buffering apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 9/351075
[patent_app_country] => US
[patent_app_date] => 1999-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 5897
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/172/06172516.pdf
[firstpage_image] =>[orig_patent_app_number] => 351075
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351075 | Output buffering apparatus and method | Jul 8, 1999 | Issued |
Array
(
[id] => 4246079
[patent_doc_number] => 06166564
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Control circuit for clock enable staging'
[patent_app_type] => 1
[patent_app_number] => 9/350734
[patent_app_country] => US
[patent_app_date] => 1999-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4680
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/166/06166564.pdf
[firstpage_image] =>[orig_patent_app_number] => 350734
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350734 | Control circuit for clock enable staging | Jul 8, 1999 | Issued |
Array
(
[id] => 4148605
[patent_doc_number] => 06122248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Data transmission system with bus failure recovery'
[patent_app_type] => 1
[patent_app_number] => 9/349918
[patent_app_country] => US
[patent_app_date] => 1999-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4745
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122248.pdf
[firstpage_image] =>[orig_patent_app_number] => 349918
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/349918 | Data transmission system with bus failure recovery | Jul 7, 1999 | Issued |
Array
(
[id] => 1463691
[patent_doc_number] => 06392915
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Method of storing and retrieving binary information'
[patent_app_type] => B1
[patent_app_number] => 09/346782
[patent_app_country] => US
[patent_app_date] => 1999-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3688
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/392/06392915.pdf
[firstpage_image] =>[orig_patent_app_number] => 09346782
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/346782 | Method of storing and retrieving binary information | Jul 6, 1999 | Issued |
Array
(
[id] => 1585333
[patent_doc_number] => 06424567
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Fast reconfigurable programmable device'
[patent_app_type] => B1
[patent_app_number] => 09/348961
[patent_app_country] => US
[patent_app_date] => 1999-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3141
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/424/06424567.pdf
[firstpage_image] =>[orig_patent_app_number] => 09348961
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348961 | Fast reconfigurable programmable device | Jul 6, 1999 | Issued |
Array
(
[id] => 4273160
[patent_doc_number] => 06259622
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Two bit per cell ROM using a two phase current sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 9/348199
[patent_app_country] => US
[patent_app_date] => 1999-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 8653
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/259/06259622.pdf
[firstpage_image] =>[orig_patent_app_number] => 348199
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348199 | Two bit per cell ROM using a two phase current sense amplifier | Jul 5, 1999 | Issued |