Trong Q Phan

Array ( [id] => 4350664 [patent_doc_number] => 06321371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Insertion of spare logic gates into the unused spaces between individual gates in standard cell artwork' [patent_app_type] => 1 [patent_app_number] => 9/346568 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9065 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321371.pdf [firstpage_image] =>[orig_patent_app_number] => 346568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159275 [patent_doc_number] => 06064587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'System and method for writing/reading data' [patent_app_type] => 1 [patent_app_number] => 9/343046 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2196 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064587.pdf [firstpage_image] =>[orig_patent_app_number] => 343046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417758 [patent_doc_number] => 06172938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Electronic instrument and semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/338597 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6499 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172938.pdf [firstpage_image] =>[orig_patent_app_number] => 338597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4165678 [patent_doc_number] => 06125057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Segmented source memory array' [patent_app_type] => 1 [patent_app_number] => 9/337147 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2887 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125057.pdf [firstpage_image] =>[orig_patent_app_number] => 337147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148000 [patent_doc_number] => 06122210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Data out buffer circuit and SRAM' [patent_app_type] => 1 [patent_app_number] => 9/335747 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3490 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122210.pdf [firstpage_image] =>[orig_patent_app_number] => 335747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204603 [patent_doc_number] => 06044014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Electronic control unit and method for storing rewrite count of nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/333994 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6329 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044014.pdf [firstpage_image] =>[orig_patent_app_number] => 333994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126785 [patent_doc_number] => 06046937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Electronic control unit and method for storing rewrite count of nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/335046 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9609 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046937.pdf [firstpage_image] =>[orig_patent_app_number] => 335046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4256869 [patent_doc_number] => 06222386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for providing a low voltage level shift' [patent_app_type] => 1 [patent_app_number] => 9/333588 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4998 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222386.pdf [firstpage_image] =>[orig_patent_app_number] => 333588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568750 [patent_doc_number] => 06339835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Pseudo-anding in dynamic logic circuits' [patent_app_type] => B1 [patent_app_number] => 09/329455 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2674 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339835.pdf [firstpage_image] =>[orig_patent_app_number] => 09329455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4389220 [patent_doc_number] => 06275969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Common case optimized circuit structure for high-performance and low-power VLSI designs' [patent_app_type] => 1 [patent_app_number] => 9/328896 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 10603 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275969.pdf [firstpage_image] =>[orig_patent_app_number] => 328896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4209402 [patent_doc_number] => 06014335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/326948 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 14976 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014335.pdf [firstpage_image] =>[orig_patent_app_number] => 326948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4196971 [patent_doc_number] => 06160734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method for ensuring security of program data in one-time programmable memory' [patent_app_type] => 1 [patent_app_number] => 9/322800 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160734.pdf [firstpage_image] =>[orig_patent_app_number] => 322800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4279838 [patent_doc_number] => 06246280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Negative voltage generating circuit with high control responsiveness which can be formed using transistor with low breakdown voltage and semiconductor memory device including the same' [patent_app_type] => 1 [patent_app_number] => 9/321884 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6402 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246280.pdf [firstpage_image] =>[orig_patent_app_number] => 321884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291212 [patent_doc_number] => 06308304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method and apparatus for realizable interconnect reduction for on-chip RC circuits' [patent_app_type] => 1 [patent_app_number] => 9/321785 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 8734 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308304.pdf [firstpage_image] =>[orig_patent_app_number] => 321785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108761 [patent_doc_number] => 06049480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Circuit for performing auto-verifying program on non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 9/317950 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3107 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049480.pdf [firstpage_image] =>[orig_patent_app_number] => 317950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120443 [patent_doc_number] => 06058045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Serial flash memory' [patent_app_type] => 1 [patent_app_number] => 9/318200 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4485 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058045.pdf [firstpage_image] =>[orig_patent_app_number] => 318200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170071 [patent_doc_number] => 06157558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Content addressable memory cell and array architectures having low transistor counts' [patent_app_type] => 1 [patent_app_number] => 9/316499 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7967 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157558.pdf [firstpage_image] =>[orig_patent_app_number] => 316499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197563 [patent_doc_number] => 06151241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Ferroelectric memory with disturb protection' [patent_app_type] => 1 [patent_app_number] => 9/314800 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 11434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151241.pdf [firstpage_image] =>[orig_patent_app_number] => 314800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6947504 [patent_doc_number] => 20010021138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'VOLTAGE GENERATOR FOR SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/313282 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7848 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021138.pdf [firstpage_image] =>[orig_patent_app_number] => 09313282 [rel_patent_id] =>[rel_patent_doc_number] =>)