Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1434074 [patent_doc_number] => 06341364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Computer assisted method of partitioning an electrical circuit' [patent_app_type] => B1 [patent_app_number] => 09/308304 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4861 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341364.pdf [firstpage_image] =>[orig_patent_app_number] => 09308304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/308304
Computer assisted method of partitioning an electrical circuit May 16, 1999 Issued
Array ( [id] => 4423134 [patent_doc_number] => 06272663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'System and method for reducing undesired radiation generated by LSI' [patent_app_type] => 1 [patent_app_number] => 9/312828 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4248 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272663.pdf [firstpage_image] =>[orig_patent_app_number] => 312828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312828
System and method for reducing undesired radiation generated by LSI May 16, 1999 Issued
09/310880 FLASH EEPROM SYSTEM May 13, 1999 Abandoned
Array ( [id] => 4291310 [patent_doc_number] => 06308311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for reconfiguring a field programmable gate array from a host' [patent_app_type] => 1 [patent_app_number] => 9/311627 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308311.pdf [firstpage_image] =>[orig_patent_app_number] => 311627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311627
Method for reconfiguring a field programmable gate array from a host May 13, 1999 Issued
Array ( [id] => 1226034 [patent_doc_number] => 06704918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Integrated circuit routing' [patent_app_type] => B1 [patent_app_number] => 09/311981 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1939 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704918.pdf [firstpage_image] =>[orig_patent_app_number] => 09311981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311981
Integrated circuit routing May 13, 1999 Issued
Array ( [id] => 4424809 [patent_doc_number] => 06266798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Multi-power supply integrated circuit evaluation system and method of operating the same' [patent_app_type] => 1 [patent_app_number] => 9/310588 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266798.pdf [firstpage_image] =>[orig_patent_app_number] => 310588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310588
Multi-power supply integrated circuit evaluation system and method of operating the same May 11, 1999 Issued
Array ( [id] => 4165983 [patent_doc_number] => 06125078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system' [patent_app_type] => 1 [patent_app_number] => 9/305748 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 48 [patent_no_of_words] => 27806 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125078.pdf [firstpage_image] =>[orig_patent_app_number] => 305748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305748
Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system May 5, 1999 Issued
Array ( [id] => 4412923 [patent_doc_number] => 06298468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Placement-based pin optimization method and apparatus for computer-aided circuit design' [patent_app_type] => 1 [patent_app_number] => 9/305802 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 6804 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298468.pdf [firstpage_image] =>[orig_patent_app_number] => 305802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305802
Placement-based pin optimization method and apparatus for computer-aided circuit design May 3, 1999 Issued
Array ( [id] => 4392773 [patent_doc_number] => 06289492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Methods and apparatuses for defining a region on an elongated object' [patent_app_type] => 1 [patent_app_number] => 9/303214 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 7509 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289492.pdf [firstpage_image] =>[orig_patent_app_number] => 303214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303214
Methods and apparatuses for defining a region on an elongated object Apr 29, 1999 Issued
Array ( [id] => 1462555 [patent_doc_number] => 06427223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method and apparatus for adaptive verification of circuit designs' [patent_app_type] => B1 [patent_app_number] => 09/303181 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 12445 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427223.pdf [firstpage_image] =>[orig_patent_app_number] => 09303181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303181
Method and apparatus for adaptive verification of circuit designs Apr 29, 1999 Issued
Array ( [id] => 4338010 [patent_doc_number] => 06249904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion' [patent_app_type] => 1 [patent_app_number] => 9/302557 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 6209 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249904.pdf [firstpage_image] =>[orig_patent_app_number] => 302557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302557
Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion Apr 29, 1999 Issued
Array ( [id] => 4423152 [patent_doc_number] => 06272665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and tool for automatically generating engineering change order' [patent_app_type] => 1 [patent_app_number] => 9/303348 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3430 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272665.pdf [firstpage_image] =>[orig_patent_app_number] => 303348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303348
Method and tool for automatically generating engineering change order Apr 28, 1999 Issued
Array ( [id] => 4318236 [patent_doc_number] => 06252814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Dummy wordline circuitry' [patent_app_type] => 1 [patent_app_number] => 9/303347 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4054 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252814.pdf [firstpage_image] =>[orig_patent_app_number] => 303347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303347
Dummy wordline circuitry Apr 28, 1999 Issued
Array ( [id] => 4145437 [patent_doc_number] => 06147915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/296547 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 7076 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147915.pdf [firstpage_image] =>[orig_patent_app_number] => 296547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296547
Semiconductor integrated circuit Apr 21, 1999 Issued
Array ( [id] => 1567749 [patent_doc_number] => 06438736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for determining cleanup line routing for components of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/293485 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11672 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438736.pdf [firstpage_image] =>[orig_patent_app_number] => 09293485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293485
Method for determining cleanup line routing for components of an integrated circuit Apr 14, 1999 Issued
Array ( [id] => 7642312 [patent_doc_number] => 06430734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for determining bus line routing for components of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/293638 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11650 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430734.pdf [firstpage_image] =>[orig_patent_app_number] => 09293638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293638
Method for determining bus line routing for components of an integrated circuit Apr 14, 1999 Issued
Array ( [id] => 1329533 [patent_doc_number] => 06606737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Method for forming a structural similarity group from a netlist of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/293484 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11672 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606737.pdf [firstpage_image] =>[orig_patent_app_number] => 09293484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293484
Method for forming a structural similarity group from a netlist of an integrated circuit Apr 14, 1999 Issued
Array ( [id] => 7622274 [patent_doc_number] => 06687892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method for determining control line routing for components of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/293488 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11673 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687892.pdf [firstpage_image] =>[orig_patent_app_number] => 09293488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293488
Method for determining control line routing for components of an integrated circuit Apr 14, 1999 Issued
Array ( [id] => 4250246 [patent_doc_number] => 06144573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Programmable logic devices with improved content addressable memory capabilities' [patent_app_type] => 1 [patent_app_number] => 9/292448 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5916 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144573.pdf [firstpage_image] =>[orig_patent_app_number] => 292448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292448
Programmable logic devices with improved content addressable memory capabilities Apr 14, 1999 Issued
Array ( [id] => 1604548 [patent_doc_number] => 06434734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for modifying placement of components of an integrated circuit by analyzing resources of adjacent components' [patent_app_type] => B1 [patent_app_number] => 09/293640 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 11648 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434734.pdf [firstpage_image] =>[orig_patent_app_number] => 09293640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293640
Method for modifying placement of components of an integrated circuit by analyzing resources of adjacent components Apr 14, 1999 Issued
Menu