Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4412946 [patent_doc_number] => 06298470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method for efficient manufacturing of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/292215 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8002 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298470.pdf [firstpage_image] =>[orig_patent_app_number] => 292215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292215
Method for efficient manufacturing of integrated circuits Apr 14, 1999 Issued
Array ( [id] => 1525059 [patent_doc_number] => 06415419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor integrated circuit device and circuit designing method therefor' [patent_app_type] => B1 [patent_app_number] => 09/291849 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5268 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415419.pdf [firstpage_image] =>[orig_patent_app_number] => 09291849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291849
Semiconductor integrated circuit device and circuit designing method therefor Apr 13, 1999 Issued
Array ( [id] => 4308973 [patent_doc_number] => 06181599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method for applying variable row BIAS to reduce program disturb in a flash memory storage array' [patent_app_type] => 1 [patent_app_number] => 9/291249 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8764 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181599.pdf [firstpage_image] =>[orig_patent_app_number] => 291249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291249
Method for applying variable row BIAS to reduce program disturb in a flash memory storage array Apr 12, 1999 Issued
Array ( [id] => 4140159 [patent_doc_number] => 06128224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for writing an erasable non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 9/289699 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8216 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128224.pdf [firstpage_image] =>[orig_patent_app_number] => 289699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289699
Method and apparatus for writing an erasable non-volatile memory Apr 8, 1999 Issued
Array ( [id] => 4423833 [patent_doc_number] => 06311310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method and apparatus for wiring integrated circuits with multiple power buses based on performance' [patent_app_type] => 1 [patent_app_number] => 9/288356 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2946 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311310.pdf [firstpage_image] =>[orig_patent_app_number] => 288356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/288356
Method and apparatus for wiring integrated circuits with multiple power buses based on performance Apr 7, 1999 Issued
Array ( [id] => 4171618 [patent_doc_number] => 06115302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Disabling a decoder for a defective element in an integrated circuit device having redundant elements' [patent_app_type] => 1 [patent_app_number] => 9/287948 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 8545 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115302.pdf [firstpage_image] =>[orig_patent_app_number] => 287948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287948
Disabling a decoder for a defective element in an integrated circuit device having redundant elements Apr 6, 1999 Issued
Array ( [id] => 1358457 [patent_doc_number] => 06580643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Nonvolatile semiconductor storage device and method for operating the same' [patent_app_type] => B1 [patent_app_number] => 09/284083 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 16437 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580643.pdf [firstpage_image] =>[orig_patent_app_number] => 09284083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/284083
Nonvolatile semiconductor storage device and method for operating the same Apr 6, 1999 Issued
Array ( [id] => 4350525 [patent_doc_number] => 06321362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy' [patent_app_type] => 1 [patent_app_number] => 9/286758 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8413 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321362.pdf [firstpage_image] =>[orig_patent_app_number] => 286758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286758
Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy Apr 5, 1999 Issued
Array ( [id] => 7646416 [patent_doc_number] => 06477104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Tiled memory and memory tile for use therein' [patent_app_type] => B1 [patent_app_number] => 09/286178 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 9397 [patent_no_of_claims] => 247 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477104.pdf [firstpage_image] =>[orig_patent_app_number] => 09286178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286178
Tiled memory and memory tile for use therein Apr 4, 1999 Issued
Array ( [id] => 4187946 [patent_doc_number] => 06084818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Semiconductor memory device capable of efficient memory cell select operation with reduced element count' [patent_app_type] => 1 [patent_app_number] => 9/283247 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 60 [patent_no_of_words] => 14461 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084818.pdf [firstpage_image] =>[orig_patent_app_number] => 283247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283247
Semiconductor memory device capable of efficient memory cell select operation with reduced element count Mar 31, 1999 Issued
Array ( [id] => 4165862 [patent_doc_number] => 06125070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Semiconductor memory device having multiple global I/O line pairs' [patent_app_type] => 1 [patent_app_number] => 9/283246 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6392 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125070.pdf [firstpage_image] =>[orig_patent_app_number] => 283246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283246
Semiconductor memory device having multiple global I/O line pairs Mar 31, 1999 Issued
Array ( [id] => 4185735 [patent_doc_number] => 06141283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state' [patent_app_type] => 1 [patent_app_number] => 9/285998 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141283.pdf [firstpage_image] =>[orig_patent_app_number] => 285998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285998
Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state Mar 31, 1999 Issued
09/280011 SEMICONDUCTOR DEVICE Mar 28, 1999 Abandoned
Array ( [id] => 4097217 [patent_doc_number] => 06026051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Low skew differential receiver with disable feature' [patent_app_type] => 1 [patent_app_number] => 9/275690 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2660 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026051.pdf [firstpage_image] =>[orig_patent_app_number] => 275690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275690
Low skew differential receiver with disable feature Mar 23, 1999 Issued
Array ( [id] => 4403143 [patent_doc_number] => 06279143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for generating a database which is used for determining the design quality of network nodes' [patent_app_type] => 1 [patent_app_number] => 9/274798 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279143.pdf [firstpage_image] =>[orig_patent_app_number] => 274798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274798
Method and apparatus for generating a database which is used for determining the design quality of network nodes Mar 22, 1999 Issued
Array ( [id] => 4204482 [patent_doc_number] => 06044006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Method for programming a ROM cell arrangement' [patent_app_type] => 1 [patent_app_number] => 9/273648 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3367 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044006.pdf [firstpage_image] =>[orig_patent_app_number] => 273648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273648
Method for programming a ROM cell arrangement Mar 22, 1999 Issued
Array ( [id] => 4337938 [patent_doc_number] => 06249899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'System and method for detecting pass FETs' [patent_app_type] => 1 [patent_app_number] => 9/273631 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249899.pdf [firstpage_image] =>[orig_patent_app_number] => 273631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273631
System and method for detecting pass FETs Mar 22, 1999 Issued
Array ( [id] => 4148070 [patent_doc_number] => 06122214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/273474 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5762 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122214.pdf [firstpage_image] =>[orig_patent_app_number] => 273474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273474
Semiconductor memory Mar 21, 1999 Issued
Array ( [id] => 4326409 [patent_doc_number] => 06253351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Circuit optimization system' [patent_app_type] => 1 [patent_app_number] => 9/273909 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5131 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253351.pdf [firstpage_image] =>[orig_patent_app_number] => 273909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273909
Circuit optimization system Mar 21, 1999 Issued
Array ( [id] => 3962035 [patent_doc_number] => 05999442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Semi-conductor device with a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/264946 [patent_app_country] => US [patent_app_date] => 1999-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2749 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999442.pdf [firstpage_image] =>[orig_patent_app_number] => 264946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264946
Semi-conductor device with a memory cell Mar 8, 1999 Issued
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