Trong Q Phan

Array ( [id] => 4416992 [patent_doc_number] => 06233192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/263050 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4686 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233192.pdf [firstpage_image] =>[orig_patent_app_number] => 263050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326494 [patent_doc_number] => 06253357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Arranging/wiring method of semiconductor device, and semiconductor device arranging/wiring apparatus capable of preventing erroneous operation of actual device, while reducing chip size' [patent_app_type] => 1 [patent_app_number] => 9/262708 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 9925 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253357.pdf [firstpage_image] =>[orig_patent_app_number] => 262708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197019 [patent_doc_number] => 06094368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Auto-tracking write and read processes for multi-bit-per-cell non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 9/262946 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7759 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094368.pdf [firstpage_image] =>[orig_patent_app_number] => 262946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305356 [patent_doc_number] => 06269468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Split I/O circuit for performance optimization of digital circuits' [patent_app_type] => 1 [patent_app_number] => 9/260453 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3372 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269468.pdf [firstpage_image] =>[orig_patent_app_number] => 260453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291236 [patent_doc_number] => 06308306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Delay route searching method and apparatus for logical circuits, and machine-readable recording medium recording program thereon' [patent_app_type] => 1 [patent_app_number] => 9/256770 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308306.pdf [firstpage_image] =>[orig_patent_app_number] => 256770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4392727 [patent_doc_number] => 06289489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method and apparatus for automatically cross-referencing graphical objects and HDL statements' [patent_app_type] => 1 [patent_app_number] => 9/256329 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289489.pdf [firstpage_image] =>[orig_patent_app_number] => 256329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4295490 [patent_doc_number] => 06324677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Integrated circuit layout design' [patent_app_type] => 1 [patent_app_number] => 9/256046 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1658 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324677.pdf [firstpage_image] =>[orig_patent_app_number] => 256046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381230 [patent_doc_number] => 06275444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/255779 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6161 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275444.pdf [firstpage_image] =>[orig_patent_app_number] => 255779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108905 [patent_doc_number] => 06049491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Bitline bias circuit for non-volatile memory devices' [patent_app_type] => 1 [patent_app_number] => 9/256648 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1813 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049491.pdf [firstpage_image] =>[orig_patent_app_number] => 256648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191992 [patent_doc_number] => 06038177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Data pipeline interrupt scheme for preventing data disturbances' [patent_app_type] => 1 [patent_app_number] => 9/253848 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038177.pdf [firstpage_image] =>[orig_patent_app_number] => 253848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4047859 [patent_doc_number] => 05995418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Circuit and method for erasing flash memory array' [patent_app_type] => 1 [patent_app_number] => 9/251040 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5157 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995418.pdf [firstpage_image] =>[orig_patent_app_number] => 251040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957061 [patent_doc_number] => 05982661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Memory device' [patent_app_type] => 1 [patent_app_number] => 9/247546 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3748 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982661.pdf [firstpage_image] =>[orig_patent_app_number] => 247546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108959 [patent_doc_number] => 06049495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Auto-programmable current limiter to control current leakage due to bitline to wordline short' [patent_app_type] => 1 [patent_app_number] => 9/243646 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3969 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049495.pdf [firstpage_image] =>[orig_patent_app_number] => 243646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4045963 [patent_doc_number] => 05943279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Semiconductor memory integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/241748 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5325 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943279.pdf [firstpage_image] =>[orig_patent_app_number] => 241748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4352611 [patent_doc_number] => 06314543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method of placing marks for alignment accuracy measurement' [patent_app_type] => 1 [patent_app_number] => 9/238884 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5116 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314543.pdf [firstpage_image] =>[orig_patent_app_number] => 238884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4389285 [patent_doc_number] => 06275974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Efficient tracing of shorts in very large nets in hierarchical designs using breadth-first search with optimal pruning' [patent_app_type] => 1 [patent_app_number] => 9/238421 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3093 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275974.pdf [firstpage_image] =>[orig_patent_app_number] => 238421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404918 [patent_doc_number] => 06263480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Efficient tracing of shorts in very large nets in hierarchical designs' [patent_app_type] => 1 [patent_app_number] => 9/238420 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3281 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263480.pdf [firstpage_image] =>[orig_patent_app_number] => 238420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4263000 [patent_doc_number] => 06222785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for refreshing a semiconductor memory using idle memory cycles' [patent_app_type] => 1 [patent_app_number] => 9/234778 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8260 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222785.pdf [firstpage_image] =>[orig_patent_app_number] => 234778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1438793 [patent_doc_number] => 06357037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Methods to securely configure an FPGA to accept selected macros' [patent_app_type] => B1 [patent_app_number] => 09/232022 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4430 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/357/06357037.pdf [firstpage_image] =>[orig_patent_app_number] => 09232022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137330 [patent_doc_number] => 06128039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Column amplifier for high fixed pattern noise reduction' [patent_app_type] => 1 [patent_app_number] => 9/228248 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 6720 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128039.pdf [firstpage_image] =>[orig_patent_app_number] => 228248 [rel_patent_id] =>[rel_patent_doc_number] =>)