Trong Q. Phan

Array ( [id] => 4424751 [patent_doc_number] => 06177893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Parallel processing analog and digital converter' [patent_app_type] => 1 [patent_app_number] => 9/153802 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10719 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177893.pdf [firstpage_image] =>[orig_patent_app_number] => 153802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4180583 [patent_doc_number] => 06140951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Double sampled switched capacitor low pass multirate filter for a .SIGMA..DELTA. D/A converter' [patent_app_type] => 1 [patent_app_number] => 9/152719 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 1596 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140951.pdf [firstpage_image] =>[orig_patent_app_number] => 152719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424575 [patent_doc_number] => 06195026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'MMX optimized data packing methodology for zero run length and variable length entropy encoding' [patent_app_type] => 1 [patent_app_number] => 9/152703 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5410 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195026.pdf [firstpage_image] =>[orig_patent_app_number] => 152703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4112395 [patent_doc_number] => 06100827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Modulation systems and methods that compensate for DC offset introduced by the digital-to-analog converter and/or the low pass filter thereof' [patent_app_type] => 1 [patent_app_number] => 9/151622 [patent_app_country] => US [patent_app_date] => 1998-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4239 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100827.pdf [firstpage_image] =>[orig_patent_app_number] => 151622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4136083 [patent_doc_number] => 06127958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Analog/digital converting circuit' [patent_app_type] => 1 [patent_app_number] => 9/150906 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4793 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127958.pdf [firstpage_image] =>[orig_patent_app_number] => 150906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4096743 [patent_doc_number] => 06026021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Semiconductor memory array partitioned into memory blocks and sub-blocks and method of addressing' [patent_app_type] => 1 [patent_app_number] => 9/151460 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9281 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026021.pdf [firstpage_image] =>[orig_patent_app_number] => 151460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126698 [patent_doc_number] => 06046931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method and apparatus for a RAM circuit having N-nary output interface' [patent_app_type] => 1 [patent_app_number] => 9/150258 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7678 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046931.pdf [firstpage_image] =>[orig_patent_app_number] => 150258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970286 [patent_doc_number] => 05936904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Device and process for reading/rewriting a dynamic random access memory cell' [patent_app_type] => 1 [patent_app_number] => 9/150255 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2416 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936904.pdf [firstpage_image] =>[orig_patent_app_number] => 150255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4193971 [patent_doc_number] => 06021074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Direct access to random redundant logic gates by using multiple short addresses' [patent_app_type] => 1 [patent_app_number] => 9/148684 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2305 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021074.pdf [firstpage_image] =>[orig_patent_app_number] => 148684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4143440 [patent_doc_number] => 06121906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Serial/parallel selective converter' [patent_app_type] => 1 [patent_app_number] => 9/145301 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 32 [patent_no_of_words] => 3335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121906.pdf [firstpage_image] =>[orig_patent_app_number] => 145301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3946971 [patent_doc_number] => 05940315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Strapped wordline architecture for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/144457 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2508 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940315.pdf [firstpage_image] =>[orig_patent_app_number] => 144457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144678 [patent_doc_number] => 06016271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Method and circuit for generating a gate voltage in non-volatile memory devices' [patent_app_type] => 1 [patent_app_number] => 9/141250 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2870 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016271.pdf [firstpage_image] =>[orig_patent_app_number] => 141250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426398 [patent_doc_number] => 06226204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/141450 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 8079 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226204.pdf [firstpage_image] =>[orig_patent_app_number] => 141450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3993849 [patent_doc_number] => 05910917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Multi-chip IC memory device with a single command controller and signal clock generator' [patent_app_type] => 1 [patent_app_number] => 9/139658 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5639 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910917.pdf [firstpage_image] =>[orig_patent_app_number] => 139658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3947328 [patent_doc_number] => 05940339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Circuit and method for a memory device with p-channel isolation gates' [patent_app_type] => 1 [patent_app_number] => 9/139852 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4416 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940339.pdf [firstpage_image] =>[orig_patent_app_number] => 139852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054332 [patent_doc_number] => 05909394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Precharge circuit for preventing invalid output pulses caused by current sensing circuits in flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/138559 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909394.pdf [firstpage_image] =>[orig_patent_app_number] => 138559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120656 [patent_doc_number] => 06058058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Memory device with a sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/137636 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2817 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058058.pdf [firstpage_image] =>[orig_patent_app_number] => 137636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170025 [patent_doc_number] => 06104635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Non-volatile memory device readable write data latch, and internal control thereof' [patent_app_type] => 1 [patent_app_number] => 9/143447 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5898 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104635.pdf [firstpage_image] =>[orig_patent_app_number] => 143447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998776 [patent_doc_number] => 05959934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Pulse wordline control circuit and method for a computer memory device' [patent_app_type] => 1 [patent_app_number] => 9/137176 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3317 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959934.pdf [firstpage_image] =>[orig_patent_app_number] => 137176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3947314 [patent_doc_number] => 05940338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Memory device with a sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/137893 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2817 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940338.pdf [firstpage_image] =>[orig_patent_app_number] => 137893 [rel_patent_id] =>[rel_patent_doc_number] =>)