Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3940002 [patent_doc_number] => 05953248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Low switching field magnetic tunneling junction for high density arrays' [patent_app_type] => 1 [patent_app_number] => 9/118979 [patent_app_country] => US [patent_app_date] => 1998-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 10 [patent_no_of_words] => 3298 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953248.pdf [firstpage_image] =>[orig_patent_app_number] => 118979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118979
Low switching field magnetic tunneling junction for high density arrays Jul 19, 1998 Issued
Array ( [id] => 3936974 [patent_doc_number] => 05946227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Magnetoresistive random access memory with shared word and digit lines' [patent_app_type] => 1 [patent_app_number] => 9/118977 [patent_app_country] => US [patent_app_date] => 1998-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2621 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946227.pdf [firstpage_image] =>[orig_patent_app_number] => 118977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/118977
Magnetoresistive random access memory with shared word and digit lines Jul 19, 1998 Issued
09/116257 DATA READ CIRCUIT Jul 15, 1998 Issued
Array ( [id] => 3994263 [patent_doc_number] => 05949737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Memory device and method for reading data therefrom' [patent_app_type] => 1 [patent_app_number] => 9/116767 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7959 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949737.pdf [firstpage_image] =>[orig_patent_app_number] => 116767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116767
Memory device and method for reading data therefrom Jul 15, 1998 Issued
09/115757 PARALLEL TEST CIRCUIT FOR MEMORY DEVICE Jul 14, 1998 Issued
Array ( [id] => 4148144 [patent_doc_number] => 06122219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Split array semiconductor graphics memory architecture supporting maskable block write operation' [patent_app_type] => 1 [patent_app_number] => 9/115377 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3985 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122219.pdf [firstpage_image] =>[orig_patent_app_number] => 115377 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115377
Split array semiconductor graphics memory architecture supporting maskable block write operation Jul 13, 1998 Issued
Array ( [id] => 4065198 [patent_doc_number] => 05970004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor memory device allowing test regardless of spare cell arrangement' [patent_app_type] => 1 [patent_app_number] => 9/114076 [patent_app_country] => US [patent_app_date] => 1998-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1994 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970004.pdf [firstpage_image] =>[orig_patent_app_number] => 114076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114076
Semiconductor memory device allowing test regardless of spare cell arrangement Jul 12, 1998 Issued
Array ( [id] => 3964259 [patent_doc_number] => 05978294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Memory cell evaluation semiconductor device, method of fabricating the same and memory cell evaluation method' [patent_app_type] => 1 [patent_app_number] => 9/112506 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 60 [patent_no_of_words] => 11974 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978294.pdf [firstpage_image] =>[orig_patent_app_number] => 112506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112506
Memory cell evaluation semiconductor device, method of fabricating the same and memory cell evaluation method Jul 8, 1998 Issued
Array ( [id] => 3925037 [patent_doc_number] => 06002609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Semiconductor device having a security circuit for preventing illegal access' [patent_app_type] => 1 [patent_app_number] => 9/111484 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5198 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002609.pdf [firstpage_image] =>[orig_patent_app_number] => 111484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111484
Semiconductor device having a security circuit for preventing illegal access Jul 7, 1998 Issued
Array ( [id] => 4246970 [patent_doc_number] => 06118682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus for reading multiple matched addresses' [patent_app_type] => 1 [patent_app_number] => 9/110872 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 4065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118682.pdf [firstpage_image] =>[orig_patent_app_number] => 110872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110872
Method and apparatus for reading multiple matched addresses Jul 6, 1998 Issued
09/111158 WAFER TEST METHOD CAPABLE OF COMPLETING A WAFER TEST IN A SHORT TIME Jul 6, 1998 Issued
Array ( [id] => 3953468 [patent_doc_number] => 05973977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Poly fuses in CMOS integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/110206 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3692 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973977.pdf [firstpage_image] =>[orig_patent_app_number] => 110206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110206
Poly fuses in CMOS integrated circuits Jul 5, 1998 Issued
Array ( [id] => 4251627 [patent_doc_number] => 06091631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed' [patent_app_type] => 1 [patent_app_number] => 9/108529 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3257 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091631.pdf [firstpage_image] =>[orig_patent_app_number] => 108529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108529
Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed Jun 30, 1998 Issued
Array ( [id] => 4368019 [patent_doc_number] => 06201746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Test method for high speed memory devices in which limit conditions for the clock are defined' [patent_app_type] => 1 [patent_app_number] => 9/107947 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201746.pdf [firstpage_image] =>[orig_patent_app_number] => 107947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107947
Test method for high speed memory devices in which limit conditions for the clock are defined Jun 29, 1998 Issued
Array ( [id] => 4337924 [patent_doc_number] => 06249898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities' [patent_app_type] => 1 [patent_app_number] => 9/109999 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8521 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249898.pdf [firstpage_image] =>[orig_patent_app_number] => 109999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109999
Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities Jun 29, 1998 Issued
Array ( [id] => 4384671 [patent_doc_number] => 06288970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Programmable logic device memory array circuit having combinable single-port memory arrays' [patent_app_type] => 1 [patent_app_number] => 9/107926 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10103 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288970.pdf [firstpage_image] =>[orig_patent_app_number] => 107926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107926
Programmable logic device memory array circuit having combinable single-port memory arrays Jun 29, 1998 Issued
Array ( [id] => 4159688 [patent_doc_number] => 06064615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Optical memory element' [patent_app_type] => 1 [patent_app_number] => 9/101024 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7190 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064615.pdf [firstpage_image] =>[orig_patent_app_number] => 101024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/101024
Optical memory element Jun 28, 1998 Issued
Array ( [id] => 4219327 [patent_doc_number] => 06028801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'High speed sensing of dual port static RAM cell' [patent_app_type] => 1 [patent_app_number] => 9/106325 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7766 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028801.pdf [firstpage_image] =>[orig_patent_app_number] => 106325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106325
High speed sensing of dual port static RAM cell Jun 28, 1998 Issued
Array ( [id] => 4017341 [patent_doc_number] => 06005794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Static memory with low power write port' [patent_app_type] => 1 [patent_app_number] => 9/106034 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3999 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005794.pdf [firstpage_image] =>[orig_patent_app_number] => 106034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106034
Static memory with low power write port Jun 25, 1998 Issued
Array ( [id] => 4026258 [patent_doc_number] => 05963505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Sequential access memory with low consumption' [patent_app_type] => 1 [patent_app_number] => 9/105560 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4942 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963505.pdf [firstpage_image] =>[orig_patent_app_number] => 105560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105560
Sequential access memory with low consumption Jun 25, 1998 Issued
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