Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4096375 [patent_doc_number] => 06018488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Semiconductor memory device and method relieving defect of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/104626 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5428 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018488.pdf [firstpage_image] =>[orig_patent_app_number] => 104626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104626
Semiconductor memory device and method relieving defect of semiconductor memory device Jun 24, 1998 Issued
09/103958 METHODS OF PROGRAMMING AND READING ONE TIME PROGRAMMABLE READ ONLY MEMORY Jun 23, 1998 Issued
Array ( [id] => 4011866 [patent_doc_number] => 05986924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'High-speed static RAM' [patent_app_type] => 1 [patent_app_number] => 9/103721 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4270 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986924.pdf [firstpage_image] =>[orig_patent_app_number] => 103721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103721
High-speed static RAM Jun 23, 1998 Issued
Array ( [id] => 3994220 [patent_doc_number] => 05949734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/103724 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 43 [patent_no_of_words] => 9199 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949734.pdf [firstpage_image] =>[orig_patent_app_number] => 103724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103724
Semiconductor memory device Jun 23, 1998 Issued
09/102659 MEMORY DEVICE FOR PERFORMING A REFRESH OPERATION UNDER AN ACTIVE MODE Jun 22, 1998 Issued
Array ( [id] => 4064875 [patent_doc_number] => 05969986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'High-bandwidth read and write architectures for non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 9/103623 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7882 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969986.pdf [firstpage_image] =>[orig_patent_app_number] => 103623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103623
High-bandwidth read and write architectures for non-volatile memories Jun 22, 1998 Issued
Array ( [id] => 4096708 [patent_doc_number] => 06026019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Two square NVRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/100729 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 3066 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026019.pdf [firstpage_image] =>[orig_patent_app_number] => 100729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100729
Two square NVRAM cell Jun 18, 1998 Issued
Array ( [id] => 4144752 [patent_doc_number] => 06016276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Semiconductor memory device which can be set one from multiple threshold value' [patent_app_type] => 1 [patent_app_number] => 9/099404 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5385 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016276.pdf [firstpage_image] =>[orig_patent_app_number] => 099404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099404
Semiconductor memory device which can be set one from multiple threshold value Jun 17, 1998 Issued
09/099160 METHOD AND APPARATUS FOR SELECTING OPTIMUM LEVELS FOR IN-SYSTEM PROGRAMMABLE CHARGE PUMPS Jun 17, 1998 Issued
Array ( [id] => 4197890 [patent_doc_number] => 06151261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Current detection type sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/099525 [patent_app_country] => US [patent_app_date] => 1998-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6645 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151261.pdf [firstpage_image] =>[orig_patent_app_number] => 099525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099525
Current detection type sense amplifier Jun 17, 1998 Issued
Array ( [id] => 3998735 [patent_doc_number] => 05959931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Memory system having multiple reading and writing ports' [patent_app_type] => 1 [patent_app_number] => 9/098429 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 7231 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959931.pdf [firstpage_image] =>[orig_patent_app_number] => 098429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098429
Memory system having multiple reading and writing ports Jun 16, 1998 Issued
Array ( [id] => 4064809 [patent_doc_number] => 05969982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Ferroelectric memory devices having linear reference cells therein and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/098485 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4109 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969982.pdf [firstpage_image] =>[orig_patent_app_number] => 098485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098485
Ferroelectric memory devices having linear reference cells therein and methods of operating same Jun 15, 1998 Issued
Array ( [id] => 3925023 [patent_doc_number] => 06002608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Ferroelectric memory and writing method of therein' [patent_app_type] => 1 [patent_app_number] => 9/094729 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1741 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002608.pdf [firstpage_image] =>[orig_patent_app_number] => 094729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094729
Ferroelectric memory and writing method of therein Jun 14, 1998 Issued
Array ( [id] => 3964390 [patent_doc_number] => 05978303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Memory device providing burst read access and write access from a single address input' [patent_app_type] => 1 [patent_app_number] => 9/096585 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 95 [patent_no_of_words] => 28922 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978303.pdf [firstpage_image] =>[orig_patent_app_number] => 096585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096585
Memory device providing burst read access and write access from a single address input Jun 11, 1998 Issued
Array ( [id] => 4120711 [patent_doc_number] => 06058062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor memory circuit' [patent_app_type] => 1 [patent_app_number] => 9/092909 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3341 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058062.pdf [firstpage_image] =>[orig_patent_app_number] => 092909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092909
Semiconductor memory circuit Jun 7, 1998 Issued
Array ( [id] => 4027303 [patent_doc_number] => 05907515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/087660 [patent_app_country] => US [patent_app_date] => 1998-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6675 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907515.pdf [firstpage_image] =>[orig_patent_app_number] => 087660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087660
Semiconductor memory device Jun 6, 1998 Issued
09/090258 METHOD AND APPARATUS FOR GLOBAL TESTING THE IMPEDANCE OF A PROGRAMMABLE ELEMENT Jun 3, 1998 Issued
Array ( [id] => 4065246 [patent_doc_number] => 05970007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/089506 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 11273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970007.pdf [firstpage_image] =>[orig_patent_app_number] => 089506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089506
Semiconductor integrated circuit device Jun 2, 1998 Issued
Array ( [id] => 4129916 [patent_doc_number] => 06033945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Multiple equilibration circuits for a single bit line' [patent_app_type] => 1 [patent_app_number] => 9/089928 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3134 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033945.pdf [firstpage_image] =>[orig_patent_app_number] => 089928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089928
Multiple equilibration circuits for a single bit line Jun 2, 1998 Issued
Array ( [id] => 3932501 [patent_doc_number] => 05914894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method for implementing a learning function' [patent_app_type] => 1 [patent_app_number] => 9/088655 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11514 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914894.pdf [firstpage_image] =>[orig_patent_app_number] => 088655 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088655
Method for implementing a learning function May 31, 1998 Issued
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