
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3939816
[patent_doc_number] => 05877986
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Multi-state Flash EEprom system on a card that includes defective cell substitution'
[patent_app_type] => 1
[patent_app_number] => 8/999472
[patent_app_country] => US
[patent_app_date] => 1997-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 9533
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/877/05877986.pdf
[firstpage_image] =>[orig_patent_app_number] => 999472
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/999472 | Multi-state Flash EEprom system on a card that includes defective cell substitution | Dec 28, 1997 | Issued |
Array
(
[id] => 3950554
[patent_doc_number] => 05930177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Buffer control circuit and method for semiconductor memory device with power saving function'
[patent_app_type] => 1
[patent_app_number] => 8/998572
[patent_app_country] => US
[patent_app_date] => 1997-12-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/930/05930177.pdf
[firstpage_image] =>[orig_patent_app_number] => 998572
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/998572 | Buffer control circuit and method for semiconductor memory device with power saving function | Dec 28, 1997 | Issued |
Array
(
[id] => 1042132
[patent_doc_number] => 06870769
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Decoder circuit used in a flash memory device'
[patent_app_type] => utility
[patent_app_number] => 08/998157
[patent_app_country] => US
[patent_app_date] => 1997-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/870/06870769.pdf
[firstpage_image] =>[orig_patent_app_number] => 08998157
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/998157 | Decoder circuit used in a flash memory device | Dec 23, 1997 | Issued |
Array
(
[id] => 3993846
[patent_doc_number] => 05862084
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/995973
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/862/05862084.pdf
[firstpage_image] =>[orig_patent_app_number] => 995973
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995973 | Semiconductor memory device | Dec 21, 1997 | Issued |
Array
(
[id] => 7646422
[patent_doc_number] => 06477098
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Dynamic random access memory array having segmented digit lines'
[patent_app_type] => B1
[patent_app_number] => 08/994906
[patent_app_country] => US
[patent_app_date] => 1997-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 6675
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[pdf_file] => patents/06/477/06477098.pdf
[firstpage_image] =>[orig_patent_app_number] => 08994906
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994906 | Dynamic random access memory array having segmented digit lines | Dec 18, 1997 | Issued |
Array
(
[id] => 3845625
[patent_doc_number] => 05815444
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Serial access system semiconductor storage device capable of reducing access time and consumption current'
[patent_app_type] => 1
[patent_app_number] => 8/995272
[patent_app_country] => US
[patent_app_date] => 1997-12-19
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[pdf_file] => patents/05/815/05815444.pdf
[firstpage_image] =>[orig_patent_app_number] => 995272
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995272 | Serial access system semiconductor storage device capable of reducing access time and consumption current | Dec 18, 1997 | Issued |
Array
(
[id] => 4218996
[patent_doc_number] => 06028781
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Selectable integrated circuit assembly and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/993806
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3595
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[pdf_file] => patents/06/028/06028781.pdf
[firstpage_image] =>[orig_patent_app_number] => 993806
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993806 | Selectable integrated circuit assembly and method of operation | Dec 17, 1997 | Issued |
Array
(
[id] => 3970874
[patent_doc_number] => 05901081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Circuit and method for preconditioning memory word lines across word line boundaries'
[patent_app_type] => 1
[patent_app_number] => 8/993875
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3892
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/901/05901081.pdf
[firstpage_image] =>[orig_patent_app_number] => 993875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993875 | Circuit and method for preconditioning memory word lines across word line boundaries | Dec 17, 1997 | Issued |
Array
(
[id] => 3962135
[patent_doc_number] => 05956267
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Self-aligned wordline keeper and method of manufacture therefor'
[patent_app_type] => 1
[patent_app_number] => 8/993009
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/956/05956267.pdf
[firstpage_image] =>[orig_patent_app_number] => 993009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993009 | Self-aligned wordline keeper and method of manufacture therefor | Dec 17, 1997 | Issued |
Array
(
[id] => 4019578
[patent_doc_number] => 05889724
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Word line driving circuit for semiconductor memory device and method'
[patent_app_type] => 1
[patent_app_number] => 8/992572
[patent_app_country] => US
[patent_app_date] => 1997-12-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/889/05889724.pdf
[firstpage_image] =>[orig_patent_app_number] => 992572
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/992572 | Word line driving circuit for semiconductor memory device and method | Dec 16, 1997 | Issued |
Array
(
[id] => 4061211
[patent_doc_number] => 05870342
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Semiconductor memory device surely reset upon power on'
[patent_app_type] => 1
[patent_app_number] => 8/990575
[patent_app_country] => US
[patent_app_date] => 1997-12-15
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[pdf_file] => patents/05/870/05870342.pdf
[firstpage_image] =>[orig_patent_app_number] => 990575
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990575 | Semiconductor memory device surely reset upon power on | Dec 14, 1997 | Issued |
Array
(
[id] => 3883095
[patent_doc_number] => 05838630
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal'
[patent_app_type] => 1
[patent_app_number] => 8/990999
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[pdf_file] => patents/05/838/05838630.pdf
[firstpage_image] =>[orig_patent_app_number] => 990999
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990999 | Integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal | Dec 14, 1997 | Issued |
Array
(
[id] => 3830544
[patent_doc_number] => 05790457
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions'
[patent_app_type] => 1
[patent_app_number] => 8/989872
[patent_app_country] => US
[patent_app_date] => 1997-12-12
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[pdf_file] => patents/05/790/05790457.pdf
[firstpage_image] =>[orig_patent_app_number] => 989872
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/989872 | Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions | Dec 11, 1997 | Issued |
Array
(
[id] => 3950513
[patent_doc_number] => 05930174
[patent_country] => US
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[patent_issue_date] => 1999-07-27
[patent_title] => 'Circuit and method for erasing flash memory array'
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[patent_app_country] => US
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[pdf_file] => patents/05/930/05930174.pdf
[firstpage_image] =>[orig_patent_app_number] => 988872
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988872 | Circuit and method for erasing flash memory array | Dec 10, 1997 | Issued |
Array
(
[id] => 3953300
[patent_doc_number] => 05973967
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Page buffer having negative voltage level shifter'
[patent_app_type] => 1
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[patent_app_country] => US
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[pdf_file] => patents/05/973/05973967.pdf
[firstpage_image] =>[orig_patent_app_number] => 985561
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/985561 | Page buffer having negative voltage level shifter | Dec 4, 1997 | Issued |
Array
(
[id] => 4187611
[patent_doc_number] => 06084793
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[patent_title] => 'Single-chip read-only memory (ROM) system'
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[patent_app_number] => 8/984092
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[pdf_file] => patents/06/084/06084793.pdf
[firstpage_image] =>[orig_patent_app_number] => 984092
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/984092 | Single-chip read-only memory (ROM) system | Dec 2, 1997 | Issued |
Array
(
[id] => 3821513
[patent_doc_number] => 05831925
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[patent_kind] => NA
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[pdf_file] => patents/05/831/05831925.pdf
[firstpage_image] =>[orig_patent_app_number] => 982672
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982672 | Memory configuration circuit and method | Dec 1, 1997 | Issued |
Array
(
[id] => 3905322
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Array
(
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Array
(
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[pdf_file] => patents/05/930/05930183.pdf
[firstpage_image] =>[orig_patent_app_number] => 978374
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978374 | Semiconductor memory device | Nov 24, 1997 | Issued |