Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6890778 [patent_doc_number] => 20010008009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-12 [patent_title] => 'Set-associative cache-management method with parallel and single-set sequential reads' [patent_app_type] => new-utility [patent_app_number] => 09/797644 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4744 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20010008009.pdf [firstpage_image] =>[orig_patent_app_number] => 09797644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797644
Set-associative cache-management method with parallel and single-set sequential reads Feb 28, 2001 Issued
Array ( [id] => 1604489 [patent_doc_number] => 06434675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for updating data stored in plural storage means in an information processing system' [patent_app_type] => B1 [patent_app_number] => 09/785003 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 8617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434675.pdf [firstpage_image] =>[orig_patent_app_number] => 09785003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785003
Method and apparatus for updating data stored in plural storage means in an information processing system Feb 14, 2001 Issued
Array ( [id] => 1234251 [patent_doc_number] => 06697911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Synchronous content addressable memory' [patent_app_type] => B2 [patent_app_number] => 09/778170 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8332 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697911.pdf [firstpage_image] =>[orig_patent_app_number] => 09778170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778170
Synchronous content addressable memory Feb 5, 2001 Issued
Array ( [id] => 430101 [patent_doc_number] => 07269090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Memory access with consecutive addresses corresponding to different rows' [patent_app_type] => utility [patent_app_number] => 09/772830 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5136 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269090.pdf [firstpage_image] =>[orig_patent_app_number] => 09772830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772830
Memory access with consecutive addresses corresponding to different rows Jan 29, 2001 Issued
Array ( [id] => 7606061 [patent_doc_number] => 07099660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'System, method and apparatus for a network-organized repository of data' [patent_app_type] => utility [patent_app_number] => 09/746503 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 31134 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099660.pdf [firstpage_image] =>[orig_patent_app_number] => 09746503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746503
System, method and apparatus for a network-organized repository of data Dec 21, 2000 Issued
Array ( [id] => 6133998 [patent_doc_number] => 20020078308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Symmetric multi-processing system' [patent_app_type] => new [patent_app_number] => 09/736585 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6141 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078308.pdf [firstpage_image] =>[orig_patent_app_number] => 09736585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736585
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism Dec 13, 2000 Issued
Array ( [id] => 1074617 [patent_doc_number] => 06839285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Page by page programmable flash memory' [patent_app_type] => utility [patent_app_number] => 09/737170 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6197 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839285.pdf [firstpage_image] =>[orig_patent_app_number] => 09737170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737170
Page by page programmable flash memory Dec 13, 2000 Issued
Array ( [id] => 1339122 [patent_doc_number] => 06601131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Flash memory access control via clock and interrupt management' [patent_app_type] => B2 [patent_app_number] => 09/735621 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8745 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601131.pdf [firstpage_image] =>[orig_patent_app_number] => 09735621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735621
Flash memory access control via clock and interrupt management Dec 13, 2000 Issued
Array ( [id] => 6973987 [patent_doc_number] => 20010003837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'Memory system having serial selection of memory devices and method' [patent_app_type] => new-utility [patent_app_number] => 09/737218 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 21860 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003837.pdf [firstpage_image] =>[orig_patent_app_number] => 09737218 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737218
System and method for assigning addresses to memory devices Dec 13, 2000 Issued
Array ( [id] => 1423595 [patent_doc_number] => 06539465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method and apparatus for byte alignment operations for a memory device that stores an odd number of bytes' [patent_app_type] => B2 [patent_app_number] => 09/736709 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539465.pdf [firstpage_image] =>[orig_patent_app_number] => 09736709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736709
Method and apparatus for byte alignment operations for a memory device that stores an odd number of bytes Dec 12, 2000 Issued
Array ( [id] => 6211534 [patent_doc_number] => 20020073273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Memory module with DRAM package for matching channel impedance' [patent_app_type] => new [patent_app_number] => 09/734853 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2020 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073273.pdf [firstpage_image] =>[orig_patent_app_number] => 09734853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734853
Memory module using DRAM package to match channel impedance Dec 10, 2000 Issued
Array ( [id] => 1250244 [patent_doc_number] => 06675268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method and apparatus for handling transfers of data volumes between controllers in a storage environment having multiple paths to the data volumes' [patent_app_type] => B1 [patent_app_number] => 09/735086 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9387 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675268.pdf [firstpage_image] =>[orig_patent_app_number] => 09735086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735086
Method and apparatus for handling transfers of data volumes between controllers in a storage environment having multiple paths to the data volumes Dec 10, 2000 Issued
Array ( [id] => 1353359 [patent_doc_number] => 06594744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Managing a snapshot volume or one or more checkpoint volumes with multiple point-in-time images in a single repository' [patent_app_type] => B1 [patent_app_number] => 09/735175 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 17606 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594744.pdf [firstpage_image] =>[orig_patent_app_number] => 09735175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735175
Managing a snapshot volume or one or more checkpoint volumes with multiple point-in-time images in a single repository Dec 10, 2000 Issued
Array ( [id] => 1135784 [patent_doc_number] => 06788604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Apparatus and method for determining the erasability of data in a memory' [patent_app_type] => B2 [patent_app_number] => 09/734411 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 18630 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788604.pdf [firstpage_image] =>[orig_patent_app_number] => 09734411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734411
Apparatus and method for determining the erasability of data in a memory Dec 10, 2000 Issued
Array ( [id] => 1129528 [patent_doc_number] => 06795878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Verifying cumulative ordering of memory instructions' [patent_app_type] => B2 [patent_app_number] => 09/734115 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8058 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795878.pdf [firstpage_image] =>[orig_patent_app_number] => 09734115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734115
Verifying cumulative ordering of memory instructions Dec 10, 2000 Issued
Array ( [id] => 1240869 [patent_doc_number] => 06691218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method and apparatus for longest match address lookup' [patent_app_type] => B2 [patent_app_number] => 09/733627 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 20277 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691218.pdf [firstpage_image] =>[orig_patent_app_number] => 09733627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733627
Method and apparatus for longest match address lookup Dec 7, 2000 Issued
Array ( [id] => 1172878 [patent_doc_number] => 06760272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method and system for supporting multiple cache configurations' [patent_app_type] => B2 [patent_app_number] => 09/731869 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2864 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760272.pdf [firstpage_image] =>[orig_patent_app_number] => 09731869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731869
Method and system for supporting multiple cache configurations Dec 6, 2000 Issued
Array ( [id] => 1564339 [patent_doc_number] => 06438063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Integrated circuit memory devices having selectable column addressing and methods of operating same' [patent_app_type] => B1 [patent_app_number] => 09/714302 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 73 [patent_no_of_words] => 31375 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438063.pdf [firstpage_image] =>[orig_patent_app_number] => 09714302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714302
Integrated circuit memory devices having selectable column addressing and methods of operating same Nov 15, 2000 Issued
Array ( [id] => 7645899 [patent_doc_number] => 06477624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Data image management via emulation of non-volatile storage device' [patent_app_type] => B1 [patent_app_number] => 09/690058 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8877 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477624.pdf [firstpage_image] =>[orig_patent_app_number] => 09690058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690058
Data image management via emulation of non-volatile storage device Oct 15, 2000 Issued
Array ( [id] => 7623783 [patent_doc_number] => 06725394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Media library with failover capability' [patent_app_type] => B1 [patent_app_number] => 09/678900 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 11144 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725394.pdf [firstpage_image] =>[orig_patent_app_number] => 09678900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/678900
Media library with failover capability Oct 1, 2000 Issued
Menu