Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1524824 [patent_doc_number] => 06415340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths' [patent_app_type] => B1 [patent_app_number] => 09/663035 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8076 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415340.pdf [firstpage_image] =>[orig_patent_app_number] => 09663035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/663035
Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths Sep 14, 2000 Issued
Array ( [id] => 1248768 [patent_doc_number] => 06678753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'IC card reading/writing apparatus and method for allowing use of multiple vendors' [patent_app_type] => B1 [patent_app_number] => 09/661391 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 20510 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678753.pdf [firstpage_image] =>[orig_patent_app_number] => 09661391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661391
IC card reading/writing apparatus and method for allowing use of multiple vendors Sep 12, 2000 Issued
Array ( [id] => 536278 [patent_doc_number] => 07191309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-13 [patent_title] => 'Double shift instruction for micro engine used in multithreaded parallel processor architecture' [patent_app_type] => utility [patent_app_number] => 10/070006 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 4513 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191309.pdf [firstpage_image] =>[orig_patent_app_number] => 10070006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/070006
Double shift instruction for micro engine used in multithreaded parallel processor architecture Aug 30, 2000 Issued
Array ( [id] => 786007 [patent_doc_number] => 06993633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-31 [patent_title] => 'Computer system utilizing speculative read requests to cache memory' [patent_app_type] => utility [patent_app_number] => 09/628718 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6204 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993633.pdf [firstpage_image] =>[orig_patent_app_number] => 09628718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628718
Computer system utilizing speculative read requests to cache memory Jul 27, 2000 Issued
Array ( [id] => 1011406 [patent_doc_number] => 06901500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method and apparatus for prefetching information and storing the information in a stream buffer' [patent_app_type] => utility [patent_app_number] => 09/627471 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7764 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901500.pdf [firstpage_image] =>[orig_patent_app_number] => 09627471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627471
Method and apparatus for prefetching information and storing the information in a stream buffer Jul 27, 2000 Issued
Array ( [id] => 1001647 [patent_doc_number] => 06912598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read' [patent_app_type] => utility [patent_app_number] => 09/627703 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3659 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912598.pdf [firstpage_image] =>[orig_patent_app_number] => 09627703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627703
Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read Jul 27, 2000 Issued
Array ( [id] => 1135849 [patent_doc_number] => 06788617 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Device for generating memory address and mobile station using the address for writing/reading data' [patent_app_type] => B1 [patent_app_number] => 09/628500 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5405 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788617.pdf [firstpage_image] =>[orig_patent_app_number] => 09628500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628500
Device for generating memory address and mobile station using the address for writing/reading data Jul 27, 2000 Issued
Array ( [id] => 702023 [patent_doc_number] => 07073014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-04 [patent_title] => 'Synchronous non-volatile memory system' [patent_app_type] => utility [patent_app_number] => 09/627682 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 15550 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/073/07073014.pdf [firstpage_image] =>[orig_patent_app_number] => 09627682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627682
Synchronous non-volatile memory system Jul 27, 2000 Issued
Array ( [id] => 1066723 [patent_doc_number] => 06851026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Synchronous flash memory with concurrent write and read operation' [patent_app_type] => utility [patent_app_number] => 09/628184 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 14079 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851026.pdf [firstpage_image] =>[orig_patent_app_number] => 09628184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628184
Synchronous flash memory with concurrent write and read operation Jul 27, 2000 Issued
Array ( [id] => 1200876 [patent_doc_number] => 06728798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Synchronous flash memory with status burst output' [patent_app_type] => B1 [patent_app_number] => 09/626190 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 35 [patent_no_of_words] => 14896 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728798.pdf [firstpage_image] =>[orig_patent_app_number] => 09626190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626190
Synchronous flash memory with status burst output Jul 27, 2000 Issued
Array ( [id] => 1030546 [patent_doc_number] => 06883044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Synchronous flash memory with simultaneous access to one or more banks' [patent_app_type] => utility [patent_app_number] => 09/627770 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 39 [patent_no_of_words] => 14969 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883044.pdf [firstpage_image] =>[orig_patent_app_number] => 09627770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627770
Synchronous flash memory with simultaneous access to one or more banks Jul 27, 2000 Issued
Array ( [id] => 1557558 [patent_doc_number] => 06401181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Dynamic allocation of physical memory space' [patent_app_type] => B1 [patent_app_number] => 09/627516 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5110 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401181.pdf [firstpage_image] =>[orig_patent_app_number] => 09627516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627516
Dynamic allocation of physical memory space Jul 27, 2000 Issued
09/627440 Information processing apparatus and storage therefor Jul 27, 2000 Abandoned
Array ( [id] => 1133965 [patent_doc_number] => 06792484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method and apparatus for storing data using a plurality of queues' [patent_app_type] => B1 [patent_app_number] => 09/627926 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792484.pdf [firstpage_image] =>[orig_patent_app_number] => 09627926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627926
Method and apparatus for storing data using a plurality of queues Jul 27, 2000 Issued
Array ( [id] => 1066736 [patent_doc_number] => 06851035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method and apparatus for storing data packets with a packet boundary indicator' [patent_app_type] => utility [patent_app_number] => 09/627800 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9246 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851035.pdf [firstpage_image] =>[orig_patent_app_number] => 09627800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627800
Method and apparatus for storing data packets with a packet boundary indicator Jul 27, 2000 Issued
Array ( [id] => 1291689 [patent_doc_number] => 06643718 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method and apparatus for controlling order dependency of items in a multiple FIFO queue structure' [patent_app_type] => B1 [patent_app_number] => 09/621070 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4827 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643718.pdf [firstpage_image] =>[orig_patent_app_number] => 09621070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621070
Method and apparatus for controlling order dependency of items in a multiple FIFO queue structure Jul 20, 2000 Issued
Array ( [id] => 1533052 [patent_doc_number] => 06480912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Method and apparatus for determining the number of empty memory locations in a FIFO memory device' [patent_app_type] => B1 [patent_app_number] => 09/621399 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3170 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480912.pdf [firstpage_image] =>[orig_patent_app_number] => 09621399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621399
Method and apparatus for determining the number of empty memory locations in a FIFO memory device Jul 20, 2000 Issued
Array ( [id] => 1481137 [patent_doc_number] => 06389524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Decoding device with associative memory permitting variable-length keyword comparisons' [patent_app_type] => B1 [patent_app_number] => 09/621531 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8454 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389524.pdf [firstpage_image] =>[orig_patent_app_number] => 09621531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621531
Decoding device with associative memory permitting variable-length keyword comparisons Jul 20, 2000 Issued
Array ( [id] => 7645925 [patent_doc_number] => 06477598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Memory controller arbitrating RAS, CAS and bank precharge signals' [patent_app_type] => B1 [patent_app_number] => 09/619858 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2765 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477598.pdf [firstpage_image] =>[orig_patent_app_number] => 09619858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619858
Memory controller arbitrating RAS, CAS and bank precharge signals Jul 19, 2000 Issued
Array ( [id] => 1488616 [patent_doc_number] => 06366514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Apparatus and method for dynamic memory refresh with multiple clocks' [patent_app_type] => B1 [patent_app_number] => 09/620032 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3154 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366514.pdf [firstpage_image] =>[orig_patent_app_number] => 09620032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620032
Apparatus and method for dynamic memory refresh with multiple clocks Jul 19, 2000 Issued
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