Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7642379 [patent_doc_number] => 06430667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Single-level store computer incorporating process-local address translation data structures' [patent_app_type] => B1 [patent_app_number] => 09/548949 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 10389 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430667.pdf [firstpage_image] =>[orig_patent_app_number] => 09548949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548949
Single-level store computer incorporating process-local address translation data structures Apr 12, 2000 Issued
Array ( [id] => 1386117 [patent_doc_number] => 06571332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method and apparatus for combined transaction reordering and buffer management' [patent_app_type] => B1 [patent_app_number] => 09/546979 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2128 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571332.pdf [firstpage_image] =>[orig_patent_app_number] => 09546979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546979
Method and apparatus for combined transaction reordering and buffer management Apr 10, 2000 Issued
Array ( [id] => 1604488 [patent_doc_number] => 06434674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Multiport memory architecture with direct data flow' [patent_app_type] => B1 [patent_app_number] => 09/542585 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434674.pdf [firstpage_image] =>[orig_patent_app_number] => 09542585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542585
Multiport memory architecture with direct data flow Apr 3, 2000 Issued
Array ( [id] => 1452260 [patent_doc_number] => 06370611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data' [patent_app_type] => B1 [patent_app_number] => 09/542624 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8282 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370611.pdf [firstpage_image] =>[orig_patent_app_number] => 09542624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542624
Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data Apr 3, 2000 Issued
Array ( [id] => 1452281 [patent_doc_number] => 06370616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Memory interface controller for datum raid operations with a datum multiplier' [patent_app_type] => B1 [patent_app_number] => 09/542760 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8966 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370616.pdf [firstpage_image] =>[orig_patent_app_number] => 09542760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542760
Memory interface controller for datum raid operations with a datum multiplier Apr 3, 2000 Issued
Array ( [id] => 1406810 [patent_doc_number] => 06560686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Memory device with variable bank partition architecture' [patent_app_type] => B1 [patent_app_number] => 09/538969 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7062 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560686.pdf [firstpage_image] =>[orig_patent_app_number] => 09538969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538969
Memory device with variable bank partition architecture Mar 30, 2000 Issued
Array ( [id] => 1452110 [patent_doc_number] => 06370577 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Information processing system having a network and a directory which may be referenced to supply information to an apparatus' [patent_app_type] => B1 [patent_app_number] => 09/518147 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 11936 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370577.pdf [firstpage_image] =>[orig_patent_app_number] => 09518147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/518147
Information processing system having a network and a directory which may be referenced to supply information to an apparatus Mar 2, 2000 Issued
Array ( [id] => 1192447 [patent_doc_number] => 06735666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method of providing direct user task access to operating system data structures' [patent_app_type] => B1 [patent_app_number] => 09/510107 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4033 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735666.pdf [firstpage_image] =>[orig_patent_app_number] => 09510107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510107
Method of providing direct user task access to operating system data structures Feb 21, 2000 Issued
Array ( [id] => 1046334 [patent_doc_number] => 06868482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method and apparatus for parallel store-in second level caching' [patent_app_type] => utility [patent_app_number] => 09/506038 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5389 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868482.pdf [firstpage_image] =>[orig_patent_app_number] => 09506038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506038
Method and apparatus for parallel store-in second level caching Feb 16, 2000 Issued
Array ( [id] => 1027645 [patent_doc_number] => 06886076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Semiconductor integrated circuit device having connection pads for superposing expansion memory' [patent_app_type] => utility [patent_app_number] => 09/497121 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4667 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/886/06886076.pdf [firstpage_image] =>[orig_patent_app_number] => 09497121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497121
Semiconductor integrated circuit device having connection pads for superposing expansion memory Feb 2, 2000 Issued
Array ( [id] => 1497765 [patent_doc_number] => 06343336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Transfer function compatibility for information for information storage reproduction' [patent_app_type] => B1 [patent_app_number] => 09/492344 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5298 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343336.pdf [firstpage_image] =>[orig_patent_app_number] => 09492344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492344
Transfer function compatibility for information for information storage reproduction Jan 26, 2000 Issued
Array ( [id] => 1339317 [patent_doc_number] => 06601153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method and apparatus for increasing computer performance through asynchronous memory block initialization' [patent_app_type] => B1 [patent_app_number] => 09/476022 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7895 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601153.pdf [firstpage_image] =>[orig_patent_app_number] => 09476022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476022
Method and apparatus for increasing computer performance through asynchronous memory block initialization Dec 30, 1999 Issued
Array ( [id] => 1308765 [patent_doc_number] => 06629206 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Set-associative cache-management using parallel reads and serial reads initiated during a wait state' [patent_app_type] => B1 [patent_app_number] => 09/476031 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3378 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629206.pdf [firstpage_image] =>[orig_patent_app_number] => 09476031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476031
Set-associative cache-management using parallel reads and serial reads initiated during a wait state Dec 30, 1999 Issued
Array ( [id] => 1521703 [patent_doc_number] => 06502166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and apparatus for distributing data across multiple disk drives' [patent_app_type] => B1 [patent_app_number] => 09/474826 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4237 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502166.pdf [firstpage_image] =>[orig_patent_app_number] => 09474826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474826
Method and apparatus for distributing data across multiple disk drives Dec 28, 1999 Issued
Array ( [id] => 4294820 [patent_doc_number] => 06324633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Division of memory into non-binary sized cache and non-cache areas' [patent_app_type] => 1 [patent_app_number] => 9/473781 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2816 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324633.pdf [firstpage_image] =>[orig_patent_app_number] => 473781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473781
Division of memory into non-binary sized cache and non-cache areas Dec 28, 1999 Issued
Array ( [id] => 6780017 [patent_doc_number] => 20030051099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'MEMORY CACHE BANK PREDICTION' [patent_app_type] => new [patent_app_number] => 09/474381 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2462 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20030051099.pdf [firstpage_image] =>[orig_patent_app_number] => 09474381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474381
Cache memory bank access prediction Dec 28, 1999 Issued
Array ( [id] => 7635008 [patent_doc_number] => 06381658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Apparatus and method to precisely position packets for a queue based memory controller' [patent_app_type] => B1 [patent_app_number] => 09/474568 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8697 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381658.pdf [firstpage_image] =>[orig_patent_app_number] => 09474568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474568
Apparatus and method to precisely position packets for a queue based memory controller Dec 28, 1999 Issued
Array ( [id] => 1452306 [patent_doc_number] => 06370625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method and apparatus for lock synchronization in a microprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/474698 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4894 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370625.pdf [firstpage_image] =>[orig_patent_app_number] => 09474698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474698
Method and apparatus for lock synchronization in a microprocessor system Dec 28, 1999 Issued
Array ( [id] => 1432286 [patent_doc_number] => 06505178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Automatic teller machine with secure variable storage for internet applications' [patent_app_type] => B1 [patent_app_number] => 09/474598 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2858 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505178.pdf [firstpage_image] =>[orig_patent_app_number] => 09474598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474598
Automatic teller machine with secure variable storage for internet applications Dec 28, 1999 Issued
Array ( [id] => 7645898 [patent_doc_number] => 06477625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method and system for reading a memory by applying control signals thereto' [patent_app_type] => B1 [patent_app_number] => 09/474932 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3491 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477625.pdf [firstpage_image] =>[orig_patent_app_number] => 09474932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474932
Method and system for reading a memory by applying control signals thereto Dec 28, 1999 Issued
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