Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4294700 [patent_doc_number] => 06324624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Read lock miss control and queue management' [patent_app_type] => 1 [patent_app_number] => 9/473798 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2948 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324624.pdf [firstpage_image] =>[orig_patent_app_number] => 473798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473798
Read lock miss control and queue management Dec 27, 1999 Issued
Array ( [id] => 1495375 [patent_doc_number] => 06418524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and apparatus for dependent segmentation and paging processing' [patent_app_type] => B1 [patent_app_number] => 09/473154 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1620 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418524.pdf [firstpage_image] =>[orig_patent_app_number] => 09473154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473154
Method and apparatus for dependent segmentation and paging processing Dec 27, 1999 Issued
Array ( [id] => 1406467 [patent_doc_number] => 06560667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Handling contiguous memory references in a multi-queue system' [patent_app_type] => B1 [patent_app_number] => 09/473112 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5957 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560667.pdf [firstpage_image] =>[orig_patent_app_number] => 09473112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473112
Handling contiguous memory references in a multi-queue system Dec 27, 1999 Issued
Array ( [id] => 1508895 [patent_doc_number] => 06466988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Multiprocessor synchronization and coherency control system' [patent_app_type] => B1 [patent_app_number] => 09/473276 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 10965 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466988.pdf [firstpage_image] =>[orig_patent_app_number] => 09473276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473276
Multiprocessor synchronization and coherency control system Dec 27, 1999 Issued
Array ( [id] => 1587375 [patent_doc_number] => 06425048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Memory pool control circuit and memory pool control method' [patent_app_type] => B1 [patent_app_number] => 09/472038 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2838 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425048.pdf [firstpage_image] =>[orig_patent_app_number] => 09472038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472038
Memory pool control circuit and memory pool control method Dec 26, 1999 Issued
Array ( [id] => 1386415 [patent_doc_number] => 06571350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Data storage method and data storage for averaging workload in a redundant storage configuration' [patent_app_type] => B1 [patent_app_number] => 09/472148 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 14135 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571350.pdf [firstpage_image] =>[orig_patent_app_number] => 09472148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472148
Data storage method and data storage for averaging workload in a redundant storage configuration Dec 26, 1999 Issued
Array ( [id] => 950305 [patent_doc_number] => 06964045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Multiple program storage within a programmable logic controller system' [patent_app_type] => utility [patent_app_number] => 09/465147 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1578 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964045.pdf [firstpage_image] =>[orig_patent_app_number] => 09465147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465147
Multiple program storage within a programmable logic controller system Dec 15, 1999 Issued
Array ( [id] => 1601938 [patent_doc_number] => 06385677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Dual interface memory card and adapter module for the same' [patent_app_type] => B1 [patent_app_number] => 09/449961 [patent_app_country] => US [patent_app_date] => 1999-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2146 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385677.pdf [firstpage_image] =>[orig_patent_app_number] => 09449961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449961
Dual interface memory card and adapter module for the same Nov 25, 1999 Issued
Array ( [id] => 1326781 [patent_doc_number] => 06609177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Method and apparatus for extending cache history' [patent_app_type] => B1 [patent_app_number] => 09/439778 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5305 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609177.pdf [firstpage_image] =>[orig_patent_app_number] => 09439778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439778
Method and apparatus for extending cache history Nov 11, 1999 Issued
Array ( [id] => 1573745 [patent_doc_number] => 06499081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method and apparatus for determining a longest prefix match in a segmented content addressable memory device' [patent_app_type] => B1 [patent_app_number] => 09/439834 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 21383 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499081.pdf [firstpage_image] =>[orig_patent_app_number] => 09439834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439834
Method and apparatus for determining a longest prefix match in a segmented content addressable memory device Nov 11, 1999 Issued
Array ( [id] => 1423479 [patent_doc_number] => 06539455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method and apparatus for determining an exact match in a ternary content addressable memory device' [patent_app_type] => B1 [patent_app_number] => 09/442042 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 20239 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539455.pdf [firstpage_image] =>[orig_patent_app_number] => 09442042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442042
Method and apparatus for determining an exact match in a ternary content addressable memory device Nov 11, 1999 Issued
Array ( [id] => 7645902 [patent_doc_number] => 06477621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Parallel access virtual channel memory system' [patent_app_type] => B1 [patent_app_number] => 09/438001 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9205 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477621.pdf [firstpage_image] =>[orig_patent_app_number] => 09438001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438001
Parallel access virtual channel memory system Nov 9, 1999 Issued
Array ( [id] => 4324541 [patent_doc_number] => 06327642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Parallel access virtual channel memory system' [patent_app_type] => 1 [patent_app_number] => 9/437810 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9131 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327642.pdf [firstpage_image] =>[orig_patent_app_number] => 437810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437810
Parallel access virtual channel memory system Nov 9, 1999 Issued
Array ( [id] => 5791452 [patent_doc_number] => 20020161965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'PIPELINED PACKET-ORIENTED MEMORY SYSTEM HAVING A UNIDIRECTIONAL COMMAND AND ADDRESS BUS AND A BIDIRECTIONAL DATA BUS' [patent_app_type] => new [patent_app_number] => 09/434082 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5013 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161965.pdf [firstpage_image] =>[orig_patent_app_number] => 09434082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434082
Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus Nov 4, 1999 Issued
Array ( [id] => 744840 [patent_doc_number] => 07035962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus' [patent_app_type] => utility [patent_app_number] => 09/434654 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5022 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035962.pdf [firstpage_image] =>[orig_patent_app_number] => 09434654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434654
Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus Nov 4, 1999 Issued
Array ( [id] => 1495238 [patent_doc_number] => 06418495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus' [patent_app_type] => B1 [patent_app_number] => 09/434731 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4999 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418495.pdf [firstpage_image] =>[orig_patent_app_number] => 09434731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434731
Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus Nov 4, 1999 Issued
Array ( [id] => 4374115 [patent_doc_number] => 06292877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Plural pipelined packet-oriented memory systems having a unidirectional command and address bus and a bidirectional data bus' [patent_app_type] => 1 [patent_app_number] => 9/434587 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4986 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292877.pdf [firstpage_image] =>[orig_patent_app_number] => 434587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434587
Plural pipelined packet-oriented memory systems having a unidirectional command and address bus and a bidirectional data bus Nov 4, 1999 Issued
Array ( [id] => 4291801 [patent_doc_number] => 06247070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Pipelined packet-oriented memory system having a undirectional command and address bus and a bidirectional data bus' [patent_app_type] => 1 [patent_app_number] => 9/434248 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4985 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247070.pdf [firstpage_image] =>[orig_patent_app_number] => 434248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434248
Pipelined packet-oriented memory system having a undirectional command and address bus and a bidirectional data bus Nov 4, 1999 Issued
Array ( [id] => 4403054 [patent_doc_number] => 06279136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Error correction code system which inhibits the transfer of padded sectors' [patent_app_type] => 1 [patent_app_number] => 9/432386 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2737 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279136.pdf [firstpage_image] =>[orig_patent_app_number] => 432386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432386
Error correction code system which inhibits the transfer of padded sectors Oct 31, 1999 Issued
Array ( [id] => 4333160 [patent_doc_number] => 06317809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Optical disk under-run protection using formatted padding sectors' [patent_app_type] => 1 [patent_app_number] => 9/431065 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2769 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317809.pdf [firstpage_image] =>[orig_patent_app_number] => 431065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431065
Optical disk under-run protection using formatted padding sectors Oct 31, 1999 Issued
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