Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4333249 [patent_doc_number] => 06332182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Disk drive control without identification fields' [patent_app_type] => 1 [patent_app_number] => 9/425535 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8562 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332182.pdf [firstpage_image] =>[orig_patent_app_number] => 425535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425535
Disk drive control without identification fields Oct 21, 1999 Issued
Array ( [id] => 4381579 [patent_doc_number] => 06256730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Apparatus and method of processing counter parameters in a digital versatile disc system' [patent_app_type] => 1 [patent_app_number] => 9/421576 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256730.pdf [firstpage_image] =>[orig_patent_app_number] => 421576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421576
Apparatus and method of processing counter parameters in a digital versatile disc system Oct 19, 1999 Issued
Array ( [id] => 7623829 [patent_doc_number] => 06725348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache' [patent_app_type] => B1 [patent_app_number] => 09/418047 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2436 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725348.pdf [firstpage_image] =>[orig_patent_app_number] => 09418047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418047
Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache Oct 12, 1999 Issued
Array ( [id] => 1058986 [patent_doc_number] => 06857058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Apparatus to map pages of disparate sizes and associated methods' [patent_app_type] => utility [patent_app_number] => 09/412077 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3482 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857058.pdf [firstpage_image] =>[orig_patent_app_number] => 09412077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412077
Apparatus to map pages of disparate sizes and associated methods Oct 3, 1999 Issued
Array ( [id] => 1508942 [patent_doc_number] => 06467000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Sideband transfer of redundancy bits for reduction of redundant cacheline transfers' [patent_app_type] => B1 [patent_app_number] => 09/411341 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5704 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467000.pdf [firstpage_image] =>[orig_patent_app_number] => 09411341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411341
Sideband transfer of redundancy bits for reduction of redundant cacheline transfers Sep 30, 1999 Issued
Array ( [id] => 4400160 [patent_doc_number] => 06304939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Token mechanism for cache-line replacement within a cache memory having redundant cache lines' [patent_app_type] => 1 [patent_app_number] => 9/404036 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2804 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304939.pdf [firstpage_image] =>[orig_patent_app_number] => 404036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404036
Token mechanism for cache-line replacement within a cache memory having redundant cache lines Sep 22, 1999 Issued
Array ( [id] => 1185839 [patent_doc_number] => 06745302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array' [patent_app_type] => B1 [patent_app_number] => 09/394039 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4892 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745302.pdf [firstpage_image] =>[orig_patent_app_number] => 09394039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394039
Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array Sep 12, 1999 Issued
Array ( [id] => 4402721 [patent_doc_number] => 06279116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation' [patent_app_type] => 1 [patent_app_number] => 9/390220 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 72 [patent_no_of_words] => 31033 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279116.pdf [firstpage_image] =>[orig_patent_app_number] => 390220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390220
Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation Sep 2, 1999 Issued
09/371840 MULTIPLE OPERATING SYSTEM CONTROLLER FOR A COMPUTER Aug 10, 1999 Abandoned
Array ( [id] => 1420704 [patent_doc_number] => 06535584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Detection and exploitation of cache redundancies' [patent_app_type] => B1 [patent_app_number] => 09/370093 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5676 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535584.pdf [firstpage_image] =>[orig_patent_app_number] => 09370093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370093
Detection and exploitation of cache redundancies Aug 5, 1999 Issued
Array ( [id] => 4325549 [patent_doc_number] => 06253298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Synchronous SRAM having pipelined enable' [patent_app_type] => 1 [patent_app_number] => 9/369035 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8828 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253298.pdf [firstpage_image] =>[orig_patent_app_number] => 369035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369035
Synchronous SRAM having pipelined enable Aug 3, 1999 Issued
Array ( [id] => 1557043 [patent_doc_number] => 06349312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method and apparatus for performing pre-allocation of memory to avoid triggering garbage collection operations' [patent_app_type] => B1 [patent_app_number] => 09/360187 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6659 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349312.pdf [firstpage_image] =>[orig_patent_app_number] => 09360187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360187
Method and apparatus for performing pre-allocation of memory to avoid triggering garbage collection operations Jul 22, 1999 Issued
Array ( [id] => 1601950 [patent_doc_number] => 06385681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Disk array control device with two different internal connection systems' [patent_app_type] => B1 [patent_app_number] => 09/358374 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11917 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385681.pdf [firstpage_image] =>[orig_patent_app_number] => 09358374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358374
Disk array control device with two different internal connection systems Jul 20, 1999 Issued
Array ( [id] => 1452234 [patent_doc_number] => 06370605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Switch based scalable performance storage architecture' [patent_app_type] => B1 [patent_app_number] => 09/358356 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15695 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370605.pdf [firstpage_image] =>[orig_patent_app_number] => 09358356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358356
Switch based scalable performance storage architecture Jul 20, 1999 Issued
Array ( [id] => 1356864 [patent_doc_number] => 06591328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Non-volatile memory storing address control table data formed of logical addresses and physical addresses' [patent_app_type] => B1 [patent_app_number] => 09/357796 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 13851 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591328.pdf [firstpage_image] =>[orig_patent_app_number] => 09357796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357796
Non-volatile memory storing address control table data formed of logical addresses and physical addresses Jul 19, 1999 Issued
Array ( [id] => 1460014 [patent_doc_number] => 06463508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method and apparatus for caching a media stream' [patent_app_type] => B1 [patent_app_number] => 09/357059 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4969 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463508.pdf [firstpage_image] =>[orig_patent_app_number] => 09357059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357059
Method and apparatus for caching a media stream Jul 18, 1999 Issued
Array ( [id] => 1085018 [patent_doc_number] => 06834325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-21 [patent_title] => 'System and method for providing client-directed staging to improve non-sequential access performance in a caching disk storage system' [patent_app_type] => B1 [patent_app_number] => 09/354482 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5488 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834325.pdf [firstpage_image] =>[orig_patent_app_number] => 09354482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354482
System and method for providing client-directed staging to improve non-sequential access performance in a caching disk storage system Jul 15, 1999 Issued
Array ( [id] => 1602324 [patent_doc_number] => 06493837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Using log buffers to trace an event in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/354840 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5205 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493837.pdf [firstpage_image] =>[orig_patent_app_number] => 09354840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354840
Using log buffers to trace an event in a computer system Jul 15, 1999 Issued
Array ( [id] => 4317685 [patent_doc_number] => 06185656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Synchronous SRAM having pipelined enable and burst address generation' [patent_app_type] => 1 [patent_app_number] => 9/516592 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8742 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185656.pdf [firstpage_image] =>[orig_patent_app_number] => 516592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516592
Synchronous SRAM having pipelined enable and burst address generation Jul 8, 1999 Issued
Array ( [id] => 4202322 [patent_doc_number] => 06094703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Synchronous SRAM having pipelined memory access enable for a burst of addresses' [patent_app_type] => 1 [patent_app_number] => 9/343121 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8751 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094703.pdf [firstpage_image] =>[orig_patent_app_number] => 343121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343121
Synchronous SRAM having pipelined memory access enable for a burst of addresses Jun 28, 1999 Issued
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