Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4349906 [patent_doc_number] => 06321321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Set-associative cache-management method with parallel and single-set sequential reads' [patent_app_type] => 1 [patent_app_number] => 9/337089 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4491 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321321.pdf [firstpage_image] =>[orig_patent_app_number] => 337089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337089
Set-associative cache-management method with parallel and single-set sequential reads Jun 20, 1999 Issued
Array ( [id] => 4204048 [patent_doc_number] => 06151664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Programmable SRAM and DRAM cache interface with preset access priorities' [patent_app_type] => 1 [patent_app_number] => 9/329134 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11855 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151664.pdf [firstpage_image] =>[orig_patent_app_number] => 329134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329134
Programmable SRAM and DRAM cache interface with preset access priorities Jun 8, 1999 Issued
Array ( [id] => 1540596 [patent_doc_number] => 06490671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'System for efficiently maintaining translation lockaside buffer consistency in a multi-threaded, multi-processor virtual memory system' [patent_app_type] => B1 [patent_app_number] => 09/321990 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4979 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490671.pdf [firstpage_image] =>[orig_patent_app_number] => 09321990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321990
System for efficiently maintaining translation lockaside buffer consistency in a multi-threaded, multi-processor virtual memory system May 27, 1999 Issued
Array ( [id] => 1546926 [patent_doc_number] => 06373770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Integrated circuit memory devices with configurable block decoder circuits' [patent_app_type] => B1 [patent_app_number] => 09/322271 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3164 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373770.pdf [firstpage_image] =>[orig_patent_app_number] => 09322271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322271
Integrated circuit memory devices with configurable block decoder circuits May 27, 1999 Issued
Array ( [id] => 1585469 [patent_doc_number] => 06424591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Network interface supporting fifo-type and SRAM-type accesses to internal buffer memory' [patent_app_type] => B1 [patent_app_number] => 09/321843 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2910 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424591.pdf [firstpage_image] =>[orig_patent_app_number] => 09321843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321843
Network interface supporting fifo-type and SRAM-type accesses to internal buffer memory May 27, 1999 Issued
Array ( [id] => 1604455 [patent_doc_number] => 06434641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme' [patent_app_type] => B1 [patent_app_number] => 09/322405 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13313 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434641.pdf [firstpage_image] =>[orig_patent_app_number] => 09322405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322405
System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme May 27, 1999 Issued
Array ( [id] => 4422630 [patent_doc_number] => 06233700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for management of cache page and medium having a cache page management program stored therein' [patent_app_type] => 1 [patent_app_number] => 9/321115 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6123 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233700.pdf [firstpage_image] =>[orig_patent_app_number] => 321115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321115
Method for management of cache page and medium having a cache page management program stored therein May 26, 1999 Issued
Array ( [id] => 1584805 [patent_doc_number] => 06449695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Data cache using plural lists to indicate sequence of data storage' [patent_app_type] => B1 [patent_app_number] => 09/321301 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 24809 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449695.pdf [firstpage_image] =>[orig_patent_app_number] => 09321301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321301
Data cache using plural lists to indicate sequence of data storage May 26, 1999 Issued
Array ( [id] => 1557571 [patent_doc_number] => 06401185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method and apparatus for accessing paged objects using a fast division technique' [patent_app_type] => B1 [patent_app_number] => 09/320578 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6744 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401185.pdf [firstpage_image] =>[orig_patent_app_number] => 09320578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320578
Method and apparatus for accessing paged objects using a fast division technique May 26, 1999 Issued
Array ( [id] => 1485061 [patent_doc_number] => 06453404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Distributed data cache with memory allocation model' [patent_app_type] => B1 [patent_app_number] => 09/321300 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 26790 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453404.pdf [firstpage_image] =>[orig_patent_app_number] => 09321300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321300
Distributed data cache with memory allocation model May 26, 1999 Issued
Array ( [id] => 1075130 [patent_doc_number] => 06839798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Flash memory capable of storing frequently rewritten data' [patent_app_type] => utility [patent_app_number] => 09/318791 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4189 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839798.pdf [firstpage_image] =>[orig_patent_app_number] => 09318791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318791
Flash memory capable of storing frequently rewritten data May 25, 1999 Issued
Array ( [id] => 1357196 [patent_doc_number] => 06591354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Separate byte control on fully synchronous pipelined SRAM' [patent_app_type] => B1 [patent_app_number] => 09/320378 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 17970 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591354.pdf [firstpage_image] =>[orig_patent_app_number] => 09320378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320378
Separate byte control on fully synchronous pipelined SRAM May 25, 1999 Issued
Array ( [id] => 4422314 [patent_doc_number] => 06272587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and apparatus for transfer of data between cache and flash memory in an internal combustion engine control system' [patent_app_type] => 1 [patent_app_number] => 9/310283 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5671 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272587.pdf [firstpage_image] =>[orig_patent_app_number] => 310283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310283
Method and apparatus for transfer of data between cache and flash memory in an internal combustion engine control system May 11, 1999 Issued
Array ( [id] => 4422535 [patent_doc_number] => 06272608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals' [patent_app_type] => 1 [patent_app_number] => 9/301422 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7709 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272608.pdf [firstpage_image] =>[orig_patent_app_number] => 301422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301422
Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals Apr 27, 1999 Issued
Array ( [id] => 1432376 [patent_doc_number] => 06505268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Data distribution in a disk array' [patent_app_type] => B1 [patent_app_number] => 09/288399 [patent_app_country] => US [patent_app_date] => 1999-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22834 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505268.pdf [firstpage_image] =>[orig_patent_app_number] => 09288399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/288399
Data distribution in a disk array Apr 7, 1999 Issued
Array ( [id] => 4402308 [patent_doc_number] => 06279088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Memory device with multiple processors having parallel access to the same memory area' [patent_app_type] => 1 [patent_app_number] => 9/275972 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6812 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279088.pdf [firstpage_image] =>[orig_patent_app_number] => 275972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275972
Memory device with multiple processors having parallel access to the same memory area Mar 24, 1999 Issued
Array ( [id] => 4324597 [patent_doc_number] => 06327646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Translation look-aside buffer utilizing high-order bits for fast access' [patent_app_type] => 1 [patent_app_number] => 9/267336 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4645 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327646.pdf [firstpage_image] =>[orig_patent_app_number] => 267336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267336
Translation look-aside buffer utilizing high-order bits for fast access Mar 11, 1999 Issued
Array ( [id] => 4297662 [patent_doc_number] => 06268975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Tape drive utilizing encoded file markers to locate target positions' [patent_app_type] => 1 [patent_app_number] => 9/266926 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5116 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268975.pdf [firstpage_image] =>[orig_patent_app_number] => 266926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266926
Tape drive utilizing encoded file markers to locate target positions Mar 11, 1999 Issued
Array ( [id] => 4236566 [patent_doc_number] => 06112231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Server to cache protocol for improved web performance' [patent_app_type] => 1 [patent_app_number] => 9/179735 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3489 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112231.pdf [firstpage_image] =>[orig_patent_app_number] => 179735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179735
Server to cache protocol for improved web performance Oct 26, 1998 Issued
Array ( [id] => 4254929 [patent_doc_number] => 06119197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method for providing and operating upgradeable cache circuitry' [patent_app_type] => 1 [patent_app_number] => 9/158179 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3109 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119197.pdf [firstpage_image] =>[orig_patent_app_number] => 158179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158179
Method for providing and operating upgradeable cache circuitry Sep 20, 1998 Issued
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