Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1496438 [patent_doc_number] => 06343036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Multi-bank dynamic random access memory devices having all bank precharge capability' [patent_app_type] => B1 [patent_app_number] => 09/157271 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 74 [patent_no_of_words] => 31315 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343036.pdf [firstpage_image] =>[orig_patent_app_number] => 09157271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/157271
Multi-bank dynamic random access memory devices having all bank precharge capability Sep 17, 1998 Issued
Array ( [id] => 4121108 [patent_doc_number] => 06052700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Calendar clock caching in a multiprocessor data processing system' [patent_app_type] => 1 [patent_app_number] => 9/156104 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 10252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052700.pdf [firstpage_image] =>[orig_patent_app_number] => 156104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156104
Calendar clock caching in a multiprocessor data processing system Sep 16, 1998 Issued
Array ( [id] => 1493312 [patent_doc_number] => 06418042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Ternary content addressable memory with compare operand selected according to mask value' [patent_app_type] => B1 [patent_app_number] => 09/150517 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13474 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418042.pdf [firstpage_image] =>[orig_patent_app_number] => 09150517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150517
Ternary content addressable memory with compare operand selected according to mask value Sep 8, 1998 Issued
Array ( [id] => 4323855 [patent_doc_number] => 06189073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method of emulating a dual-port memory device using an internally cached static random access memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/139928 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3718 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189073.pdf [firstpage_image] =>[orig_patent_app_number] => 139928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139928
Method of emulating a dual-port memory device using an internally cached static random access memory architecture Aug 25, 1998 Issued
Array ( [id] => 4335333 [patent_doc_number] => 06243799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytes' [patent_app_type] => 1 [patent_app_number] => 9/130569 [patent_app_country] => US [patent_app_date] => 1998-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243799.pdf [firstpage_image] =>[orig_patent_app_number] => 130569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/130569
Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytes Aug 6, 1998 Issued
Array ( [id] => 4424777 [patent_doc_number] => 06230249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Methods and apparatus for providing logical cell available information in a memory' [patent_app_type] => 1 [patent_app_number] => 9/130065 [patent_app_country] => US [patent_app_date] => 1998-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7318 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230249.pdf [firstpage_image] =>[orig_patent_app_number] => 130065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/130065
Methods and apparatus for providing logical cell available information in a memory Aug 6, 1998 Issued
Array ( [id] => 4159703 [patent_doc_number] => 06064616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Conditional restore for SRAM' [patent_app_type] => 1 [patent_app_number] => 9/128018 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4487 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064616.pdf [firstpage_image] =>[orig_patent_app_number] => 128018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128018
Conditional restore for SRAM Jul 29, 1998 Issued
Array ( [id] => 4170123 [patent_doc_number] => 06108255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry' [patent_app_type] => 1 [patent_app_number] => 9/128017 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4490 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108255.pdf [firstpage_image] =>[orig_patent_app_number] => 128017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128017
Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry Jul 29, 1998 Issued
Array ( [id] => 1519669 [patent_doc_number] => 06421770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Buffer memory configuration having a memory between a USB and a CPU' [patent_app_type] => B1 [patent_app_number] => 09/120160 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6405 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421770.pdf [firstpage_image] =>[orig_patent_app_number] => 09120160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120160
Buffer memory configuration having a memory between a USB and a CPU Jul 20, 1998 Issued
Array ( [id] => 4177654 [patent_doc_number] => 06108750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Simultaneous read/write control of data storage disk units' [patent_app_type] => 1 [patent_app_number] => 9/116344 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 14492 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108750.pdf [firstpage_image] =>[orig_patent_app_number] => 116344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116344
Simultaneous read/write control of data storage disk units Jul 15, 1998 Issued
Array ( [id] => 4201862 [patent_doc_number] => 06094674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Information processing system and information processing method and quality of service supplying method for use with the system' [patent_app_type] => 1 [patent_app_number] => 9/106291 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 11893 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094674.pdf [firstpage_image] =>[orig_patent_app_number] => 106291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106291
Information processing system and information processing method and quality of service supplying method for use with the system Jun 28, 1998 Issued
09/098037 SYNCHRONOUS SRAM HAVING PIPELINED ENABLE Jun 14, 1998 Abandoned
Array ( [id] => 1098383 [patent_doc_number] => RE038651 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Variable depth and width memory device' [patent_app_type] => E1 [patent_app_number] => 09/096917 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3681 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038651.pdf [firstpage_image] =>[orig_patent_app_number] => 09096917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096917
Variable depth and width memory device Jun 11, 1998 Issued
09/082655 INTERCHANGEABLE CARTRIDGE DATA STORAGE SYSTEM FOR DEVICES PERFORMING DIVERSE FUNCTIONS May 20, 1998 Abandoned
Array ( [id] => 4200010 [patent_doc_number] => 06021474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Apparatus and method of snooping processors and look-aside caches' [patent_app_type] => 1 [patent_app_number] => 9/076798 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3359 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021474.pdf [firstpage_image] =>[orig_patent_app_number] => 076798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076798
Apparatus and method of snooping processors and look-aside caches May 12, 1998 Issued
Array ( [id] => 1425237 [patent_doc_number] => 06535960 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Partitioned cache memory with switchable access paths' [patent_app_type] => B1 [patent_app_number] => 09/074317 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 6653 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535960.pdf [firstpage_image] =>[orig_patent_app_number] => 09074317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074317
Partitioned cache memory with switchable access paths May 7, 1998 Issued
Array ( [id] => 4148672 [patent_doc_number] => 06016530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Mass computer storage system having both solid state and rotating disk types of memory' [patent_app_type] => 1 [patent_app_number] => 9/063748 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4321 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016530.pdf [firstpage_image] =>[orig_patent_app_number] => 063748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063748
Mass computer storage system having both solid state and rotating disk types of memory Apr 20, 1998 Issued
Array ( [id] => 4126710 [patent_doc_number] => 06058455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'RAID system having a selectable unattended mode of operation with conditional and hierarchical automatic re-configuration' [patent_app_type] => 1 [patent_app_number] => 9/049167 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 9653 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058455.pdf [firstpage_image] =>[orig_patent_app_number] => 049167 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049167
RAID system having a selectable unattended mode of operation with conditional and hierarchical automatic re-configuration Mar 26, 1998 Issued
Array ( [id] => 4025160 [patent_doc_number] => 06006308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Removable library media system utilizing redundant data storage and error detection and correction' [patent_app_type] => 1 [patent_app_number] => 9/042149 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10636 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006308.pdf [firstpage_image] =>[orig_patent_app_number] => 042149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042149
Removable library media system utilizing redundant data storage and error detection and correction Mar 12, 1998 Issued
Array ( [id] => 4345519 [patent_doc_number] => 06330591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network' [patent_app_type] => 1 [patent_app_number] => 9/036897 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3952 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330591.pdf [firstpage_image] =>[orig_patent_app_number] => 036897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/036897
High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network Mar 8, 1998 Issued
Menu