Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7642375 [patent_doc_number] => 06430671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Address generation utilizing an adder, a non-sequential counter and a latch' [patent_app_type] => B1 [patent_app_number] => 09/021319 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 20216 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430671.pdf [firstpage_image] =>[orig_patent_app_number] => 09021319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021319
Address generation utilizing an adder, a non-sequential counter and a latch Feb 9, 1998 Issued
Array ( [id] => 1411807 [patent_doc_number] => 06553476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Storage management based on predicted I/O execution times' [patent_app_type] => B1 [patent_app_number] => 09/020929 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 24468 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553476.pdf [firstpage_image] =>[orig_patent_app_number] => 09020929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020929
Storage management based on predicted I/O execution times Feb 8, 1998 Issued
Array ( [id] => 4120957 [patent_doc_number] => 06023720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Simultaneous processing of read and write requests using optimized storage partitions for read and write request deadlines' [patent_app_type] => 1 [patent_app_number] => 9/020883 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11316 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023720.pdf [firstpage_image] =>[orig_patent_app_number] => 020883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020883
Simultaneous processing of read and write requests using optimized storage partitions for read and write request deadlines Feb 8, 1998 Issued
Array ( [id] => 4373991 [patent_doc_number] => 06292870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units' [patent_app_type] => 1 [patent_app_number] => 9/020678 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 67 [patent_no_of_words] => 11015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292870.pdf [firstpage_image] =>[orig_patent_app_number] => 020678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020678
Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units Feb 8, 1998 Issued
Array ( [id] => 4237283 [patent_doc_number] => 06112280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method and apparatus for distinct instruction pointer storage in a partitioned cache memory' [patent_app_type] => 1 [patent_app_number] => 9/003568 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3408 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112280.pdf [firstpage_image] =>[orig_patent_app_number] => 003568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003568
Method and apparatus for distinct instruction pointer storage in a partitioned cache memory Jan 5, 1998 Issued
Array ( [id] => 4414851 [patent_doc_number] => 06172670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for simultaneous shape-dependent access to picture data stored at a plurality of addresses' [patent_app_type] => 1 [patent_app_number] => 8/930384 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6069 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172670.pdf [firstpage_image] =>[orig_patent_app_number] => 930384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/930384
Method and apparatus for simultaneous shape-dependent access to picture data stored at a plurality of addresses Jan 4, 1998 Issued
Array ( [id] => 4152390 [patent_doc_number] => 06148364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method and apparatus for cascading content addressable memory devices' [patent_app_type] => 1 [patent_app_number] => 9/001110 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6019 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148364.pdf [firstpage_image] =>[orig_patent_app_number] => 001110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001110
Method and apparatus for cascading content addressable memory devices Dec 29, 1997 Issued
Array ( [id] => 6282489 [patent_doc_number] => 20020107877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'SYSTEM FOR BACKING UP FILES FROM DISK VOLUMES ON MULTIPLE NODES OF A COMPUTER NETWORK' [patent_app_type] => new [patent_app_number] => 08/999215 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 23364 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20020107877.pdf [firstpage_image] =>[orig_patent_app_number] => 08999215 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999215
SYSTEM FOR BACKING UP FILES FROM DISK VOLUMES ON MULTIPLE NODES OF A COMPUTER NETWORK Dec 28, 1997 Abandoned
Array ( [id] => 4019598 [patent_doc_number] => 05860101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory' [patent_app_type] => 1 [patent_app_number] => 8/992785 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3509 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860101.pdf [firstpage_image] =>[orig_patent_app_number] => 992785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992785
Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory Dec 16, 1997 Issued
Array ( [id] => 3815767 [patent_doc_number] => 05829030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'System for performing cache flush transactions from interconnected processor modules to paired memory modules' [patent_app_type] => 1 [patent_app_number] => 8/992757 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9896 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829030.pdf [firstpage_image] =>[orig_patent_app_number] => 992757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992757
System for performing cache flush transactions from interconnected processor modules to paired memory modules Dec 16, 1997 Issued
Array ( [id] => 4011691 [patent_doc_number] => 05893163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system' [patent_app_type] => 1 [patent_app_number] => 8/992135 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893163.pdf [firstpage_image] =>[orig_patent_app_number] => 992135 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992135
Method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system Dec 16, 1997 Issued
Array ( [id] => 6675942 [patent_doc_number] => 20030061545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING TEST MODE ACCESS TO AN INSTRUCTION CACHE AND MICROCODE ROM' [patent_app_type] => new [patent_app_number] => 08/988616 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6493 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061545.pdf [firstpage_image] =>[orig_patent_app_number] => 08988616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988616
METHOD AND APPARATUS FOR PROVIDING TEST MODE ACCESS TO AN INSTRUCTION CACHE AND MICROCODE ROM Dec 10, 1997 Abandoned
Array ( [id] => 4224032 [patent_doc_number] => 06079005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address' [patent_app_type] => 1 [patent_app_number] => 8/975224 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13894 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079005.pdf [firstpage_image] =>[orig_patent_app_number] => 975224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975224
Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address Nov 19, 1997 Issued
Array ( [id] => 4211321 [patent_doc_number] => 06044437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Method for generating and transferring redundancy bits between levels of a cache memory hierarchy' [patent_app_type] => 1 [patent_app_number] => 8/968059 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5752 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044437.pdf [firstpage_image] =>[orig_patent_app_number] => 968059 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968059
Method for generating and transferring redundancy bits between levels of a cache memory hierarchy Nov 11, 1997 Issued
Array ( [id] => 1434052 [patent_doc_number] => 06341342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method and apparatus for zeroing a transfer buffer memory as a background task' [patent_app_type] => B1 [patent_app_number] => 08/963862 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9443 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341342.pdf [firstpage_image] =>[orig_patent_app_number] => 08963862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963862
Method and apparatus for zeroing a transfer buffer memory as a background task Nov 3, 1997 Issued
Array ( [id] => 4151878 [patent_doc_number] => 06035383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Memory access request result prediction prior to confirm signal generation' [patent_app_type] => 1 [patent_app_number] => 8/962832 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035383.pdf [firstpage_image] =>[orig_patent_app_number] => 962832 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962832
Memory access request result prediction prior to confirm signal generation Nov 2, 1997 Issued
Array ( [id] => 1337006 [patent_doc_number] => 06604165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Library control device for logically dividing and controlling library device and method thereof' [patent_app_type] => B1 [patent_app_number] => 08/962392 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 18280 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604165.pdf [firstpage_image] =>[orig_patent_app_number] => 08962392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962392
Library control device for logically dividing and controlling library device and method thereof Oct 30, 1997 Issued
Array ( [id] => 4162382 [patent_doc_number] => 06032234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Clustered multiprocessor system having main memory mapping shared expansion memory addresses and their accessibility states' [patent_app_type] => 1 [patent_app_number] => 8/962335 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4820 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032234.pdf [firstpage_image] =>[orig_patent_app_number] => 962335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962335
Clustered multiprocessor system having main memory mapping shared expansion memory addresses and their accessibility states Oct 30, 1997 Issued
Array ( [id] => 4316298 [patent_doc_number] => 06199140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Multiport content addressable memory device and timing signals' [patent_app_type] => 1 [patent_app_number] => 8/967314 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8266 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199140.pdf [firstpage_image] =>[orig_patent_app_number] => 967314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967314
Multiport content addressable memory device and timing signals Oct 29, 1997 Issued
Array ( [id] => 4424768 [patent_doc_number] => 06230247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and apparatus for adaptive storage space allocation' [patent_app_type] => 1 [patent_app_number] => 8/960570 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3819 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230247.pdf [firstpage_image] =>[orig_patent_app_number] => 960570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960570
Method and apparatus for adaptive storage space allocation Oct 28, 1997 Issued
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