Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4151754 [patent_doc_number] => 06035376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'System and method for changing the states of directory-based caches and memories from read/write to read-only' [patent_app_type] => 1 [patent_app_number] => 8/967342 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6428 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035376.pdf [firstpage_image] =>[orig_patent_app_number] => 967342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967342
System and method for changing the states of directory-based caches and memories from read/write to read-only Oct 20, 1997 Issued
Array ( [id] => 4199021 [patent_doc_number] => 06038638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Pausing and resuming applications running in a data processing system using tape location parameters and pipes' [patent_app_type] => 1 [patent_app_number] => 8/953575 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2923 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038638.pdf [firstpage_image] =>[orig_patent_app_number] => 953575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953575
Pausing and resuming applications running in a data processing system using tape location parameters and pipes Oct 16, 1997 Issued
Array ( [id] => 4162493 [patent_doc_number] => 06032242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Methods and systems for generating alternate and zigzag address scans based on feedback addresses of alternate and zigzag access patterns' [patent_app_type] => 1 [patent_app_number] => 8/950968 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 4822 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032242.pdf [firstpage_image] =>[orig_patent_app_number] => 950968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950968
Methods and systems for generating alternate and zigzag address scans based on feedback addresses of alternate and zigzag access patterns Oct 14, 1997 Issued
Array ( [id] => 4085265 [patent_doc_number] => 06009500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Replacement of erroneous firmware in a redundant non-volatile memory system' [patent_app_type] => 1 [patent_app_number] => 8/950327 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3491 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009500.pdf [firstpage_image] =>[orig_patent_app_number] => 950327 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950327
Replacement of erroneous firmware in a redundant non-volatile memory system Oct 13, 1997 Issued
Array ( [id] => 4088763 [patent_doc_number] => 06070232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Cache controller fault tolerant computer and data transfer system setting recovery points' [patent_app_type] => 1 [patent_app_number] => 8/948430 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9895 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070232.pdf [firstpage_image] =>[orig_patent_app_number] => 948430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948430
Cache controller fault tolerant computer and data transfer system setting recovery points Oct 9, 1997 Issued
Array ( [id] => 4422717 [patent_doc_number] => 06272625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Apparatus and method for processing events in a digital versatile disc (DVD) system using system threads and separate dormant/awake counter threads and clock driven semaphores' [patent_app_type] => 1 [patent_app_number] => 8/946847 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4618 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272625.pdf [firstpage_image] =>[orig_patent_app_number] => 946847 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946847
Apparatus and method for processing events in a digital versatile disc (DVD) system using system threads and separate dormant/awake counter threads and clock driven semaphores Oct 7, 1997 Issued
Array ( [id] => 4155948 [patent_doc_number] => 06122712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel' [patent_app_type] => 1 [patent_app_number] => 8/946061 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122712.pdf [firstpage_image] =>[orig_patent_app_number] => 946061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946061
Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel Oct 6, 1997 Issued
Array ( [id] => 4270055 [patent_doc_number] => 06223249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Apparatus and method for controlling access to one or more disc storage devices' [patent_app_type] => 1 [patent_app_number] => 8/944093 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 7619 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223249.pdf [firstpage_image] =>[orig_patent_app_number] => 944093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944093
Apparatus and method for controlling access to one or more disc storage devices Oct 1, 1997 Issued
Array ( [id] => 4312791 [patent_doc_number] => 06237108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Multiprocessor system having redundant shared memory configuration' [patent_app_type] => 1 [patent_app_number] => 8/942724 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 10767 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237108.pdf [firstpage_image] =>[orig_patent_app_number] => 942724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942724
Multiprocessor system having redundant shared memory configuration Oct 1, 1997 Issued
Array ( [id] => 4403866 [patent_doc_number] => 06263401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method and apparatus for transferring data between a register stack and a memory resource' [patent_app_type] => 1 [patent_app_number] => 8/940834 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4142 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263401.pdf [firstpage_image] =>[orig_patent_app_number] => 940834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940834
Method and apparatus for transferring data between a register stack and a memory resource Sep 29, 1997 Issued
Array ( [id] => 4088310 [patent_doc_number] => 06070201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Alternate selection of virtual data buffer pathways' [patent_app_type] => 1 [patent_app_number] => 8/937798 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8805 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070201.pdf [firstpage_image] =>[orig_patent_app_number] => 937798 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937798
Alternate selection of virtual data buffer pathways Sep 24, 1997 Issued
Array ( [id] => 4256990 [patent_doc_number] => 06081876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Memory error containment in network cache environment via restricted access' [patent_app_type] => 1 [patent_app_number] => 8/935242 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2608 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081876.pdf [firstpage_image] =>[orig_patent_app_number] => 935242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935242
Memory error containment in network cache environment via restricted access Sep 21, 1997 Issued
Array ( [id] => 4123913 [patent_doc_number] => 06101577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Pipelined instruction cache and branch prediction mechanism therefor' [patent_app_type] => 1 [patent_app_number] => 8/929767 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9786 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101577.pdf [firstpage_image] =>[orig_patent_app_number] => 929767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929767
Pipelined instruction cache and branch prediction mechanism therefor Sep 14, 1997 Issued
Array ( [id] => 4147726 [patent_doc_number] => 06128718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size' [patent_app_type] => 1 [patent_app_number] => 8/919376 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5174 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128718.pdf [firstpage_image] =>[orig_patent_app_number] => 919376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919376
Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size Aug 27, 1997 Issued
Array ( [id] => 7095074 [patent_doc_number] => 20010034814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'CACHING WEB RESOURCES USING VARIED REPLACEMENT STTRATEGIES AND STORAGE' [patent_app_type] => new [patent_app_number] => 08/918726 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6589 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034814.pdf [firstpage_image] =>[orig_patent_app_number] => 08918726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918726
CACHING WEB RESOURCES USING VARIED REPLACEMENT STTRATEGIES AND STORAGE Aug 20, 1997 Abandoned
Array ( [id] => 4047887 [patent_doc_number] => 05995420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Integrated XNOR flip-flop for cache tag comparison' [patent_app_type] => 1 [patent_app_number] => 8/915001 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5373 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995420.pdf [firstpage_image] =>[orig_patent_app_number] => 915001 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915001
Integrated XNOR flip-flop for cache tag comparison Aug 19, 1997 Issued
Array ( [id] => 4059937 [patent_doc_number] => 05875486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Semiconductor memory device with clock timing to activate memory cells for subsequent access' [patent_app_type] => 1 [patent_app_number] => 8/912071 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9012 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875486.pdf [firstpage_image] =>[orig_patent_app_number] => 912071 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912071
Semiconductor memory device with clock timing to activate memory cells for subsequent access Aug 14, 1997 Issued
Array ( [id] => 4110048 [patent_doc_number] => 06134638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Memory controller supporting DRAM circuits with different operating speeds' [patent_app_type] => 1 [patent_app_number] => 8/910847 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6973 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134638.pdf [firstpage_image] =>[orig_patent_app_number] => 910847 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910847
Memory controller supporting DRAM circuits with different operating speeds Aug 12, 1997 Issued
Array ( [id] => 3795278 [patent_doc_number] => 05809340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Adaptively generating timing signals for access to various memory devices based on stored profiles' [patent_app_type] => 1 [patent_app_number] => 8/909745 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 19351 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809340.pdf [firstpage_image] =>[orig_patent_app_number] => 909745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909745
Adaptively generating timing signals for access to various memory devices based on stored profiles Aug 11, 1997 Issued
Array ( [id] => 4057436 [patent_doc_number] => 05996052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array' [patent_app_type] => 1 [patent_app_number] => 8/905565 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4843 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996052.pdf [firstpage_image] =>[orig_patent_app_number] => 905565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905565
Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array Aug 3, 1997 Issued
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