
Troy Chambers
Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )
| Most Active Art Unit | 3641 |
| Art Unit(s) | 3658, 3641 |
| Total Applications | 1158 |
| Issued Applications | 719 |
| Pending Applications | 123 |
| Abandoned Applications | 316 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4323969
[patent_doc_number] => 06189081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Non-volatile semiconductor storage with memory requirement and availability comparison means and method'
[patent_app_type] => 1
[patent_app_number] => 8/862373
[patent_app_country] => US
[patent_app_date] => 1997-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 7230
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 393
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/189/06189081.pdf
[firstpage_image] =>[orig_patent_app_number] => 862373
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/862373 | Non-volatile semiconductor storage with memory requirement and availability comparison means and method | May 22, 1997 | Issued |
Array
(
[id] => 4223712
[patent_doc_number] => 06078983
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Multiprocessor system having distinct data bus and address bus arbiters'
[patent_app_type] => 1
[patent_app_number] => 8/862322
[patent_app_country] => US
[patent_app_date] => 1997-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6693
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078983.pdf
[firstpage_image] =>[orig_patent_app_number] => 862322
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/862322 | Multiprocessor system having distinct data bus and address bus arbiters | May 22, 1997 | Issued |
Array
(
[id] => 4374005
[patent_doc_number] => 06175891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'System and method for assigning addresses to memory devices'
[patent_app_type] => 1
[patent_app_number] => 8/842030
[patent_app_country] => US
[patent_app_date] => 1997-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 44
[patent_no_of_words] => 21324
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/175/06175891.pdf
[firstpage_image] =>[orig_patent_app_number] => 842030
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/842030 | System and method for assigning addresses to memory devices | Apr 22, 1997 | Issued |
| 08/840536 | CUSTOMIZED MUSIC DISTRIBUTION AND PLAYBACK SYSTEM | Apr 21, 1997 | Abandoned |
Array
(
[id] => 3759057
[patent_doc_number] => 05787489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Synchronous SRAM having pipelined enable'
[patent_app_type] => 1
[patent_app_number] => 8/825963
[patent_app_country] => US
[patent_app_date] => 1997-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8750
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/787/05787489.pdf
[firstpage_image] =>[orig_patent_app_number] => 825963
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/825963 | Synchronous SRAM having pipelined enable | Apr 3, 1997 | Issued |
Array
(
[id] => 4206681
[patent_doc_number] => 06131144
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Stack caching method with overflow/underflow control using pointers'
[patent_app_type] => 1
[patent_app_number] => 8/828769
[patent_app_country] => US
[patent_app_date] => 1997-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 15176
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/131/06131144.pdf
[firstpage_image] =>[orig_patent_app_number] => 828769
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/828769 | Stack caching method with overflow/underflow control using pointers | Mar 31, 1997 | Issued |
Array
(
[id] => 3815720
[patent_doc_number] => 05829027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Removable processor board having first, second and third level cache system for use in a multiprocessor computer system'
[patent_app_type] => 1
[patent_app_number] => 8/828868
[patent_app_country] => US
[patent_app_date] => 1997-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 10095
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/829/05829027.pdf
[firstpage_image] =>[orig_patent_app_number] => 828868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/828868 | Removable processor board having first, second and third level cache system for use in a multiprocessor computer system | Mar 30, 1997 | Issued |
Array
(
[id] => 4260222
[patent_doc_number] => 06167488
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Stack caching circuit with overflow/underflow unit'
[patent_app_type] => 1
[patent_app_number] => 8/828899
[patent_app_country] => US
[patent_app_date] => 1997-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 15170
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/167/06167488.pdf
[firstpage_image] =>[orig_patent_app_number] => 828899
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/828899 | Stack caching circuit with overflow/underflow unit | Mar 30, 1997 | Issued |
Array
(
[id] => 4199108
[patent_doc_number] => 06038644
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Multiprocessor system with partial broadcast capability of a cache coherent processing request'
[patent_app_type] => 1
[patent_app_number] => 8/820831
[patent_app_country] => US
[patent_app_date] => 1997-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 16149
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/038/06038644.pdf
[firstpage_image] =>[orig_patent_app_number] => 820831
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/820831 | Multiprocessor system with partial broadcast capability of a cache coherent processing request | Mar 18, 1997 | Issued |
Array
(
[id] => 1587367
[patent_doc_number] => 06425046
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Method for using a latched sense amplifier in a memory module as a high-speed cache memory'
[patent_app_type] => B1
[patent_app_number] => 08/820297
[patent_app_country] => US
[patent_app_date] => 1997-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 30
[patent_no_of_words] => 10646
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/425/06425046.pdf
[firstpage_image] =>[orig_patent_app_number] => 08820297
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/820297 | Method for using a latched sense amplifier in a memory module as a high-speed cache memory | Mar 17, 1997 | Issued |
Array
(
[id] => 3913478
[patent_doc_number] => 05835956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Synchronous dram having a plurality of latency modes'
[patent_app_type] => 1
[patent_app_number] => 8/822148
[patent_app_country] => US
[patent_app_date] => 1997-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 66
[patent_figures_cnt] => 74
[patent_no_of_words] => 30182
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/835/05835956.pdf
[firstpage_image] =>[orig_patent_app_number] => 822148
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/822148 | Synchronous dram having a plurality of latency modes | Mar 16, 1997 | Issued |
Array
(
[id] => 4085803
[patent_doc_number] => 06009537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Disk wear prevention by relocating data in response to a head slide count'
[patent_app_type] => 1
[patent_app_number] => 8/818980
[patent_app_country] => US
[patent_app_date] => 1997-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4467
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/009/06009537.pdf
[firstpage_image] =>[orig_patent_app_number] => 818980
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/818980 | Disk wear prevention by relocating data in response to a head slide count | Mar 13, 1997 | Issued |
Array
(
[id] => 4121404
[patent_doc_number] => 06023750
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Microcontroller having dedicated hardware for memory address space expansion via auxilliary address signal generation'
[patent_app_type] => 1
[patent_app_number] => 8/812551
[patent_app_country] => US
[patent_app_date] => 1997-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 7579
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/023/06023750.pdf
[firstpage_image] =>[orig_patent_app_number] => 812551
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/812551 | Microcontroller having dedicated hardware for memory address space expansion via auxilliary address signal generation | Mar 6, 1997 | Issued |
Array
(
[id] => 4209039
[patent_doc_number] => 06154825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations'
[patent_app_type] => 1
[patent_app_number] => 8/814733
[patent_app_country] => US
[patent_app_date] => 1997-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4709
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/154/06154825.pdf
[firstpage_image] =>[orig_patent_app_number] => 814733
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/814733 | Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations | Mar 6, 1997 | Issued |
Array
(
[id] => 1353111
[patent_doc_number] => 06594728
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Cache memory with dual-way arrays and multiplexed parallel output'
[patent_app_type] => B1
[patent_app_number] => 08/813500
[patent_app_country] => US
[patent_app_date] => 1997-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 14133
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/594/06594728.pdf
[firstpage_image] =>[orig_patent_app_number] => 08813500
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/813500 | Cache memory with dual-way arrays and multiplexed parallel output | Mar 6, 1997 | Issued |
Array
(
[id] => 1353111
[patent_doc_number] => 06594728
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Cache memory with dual-way arrays and multiplexed parallel output'
[patent_app_type] => B1
[patent_app_number] => 08/813500
[patent_app_country] => US
[patent_app_date] => 1997-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 14133
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/594/06594728.pdf
[firstpage_image] =>[orig_patent_app_number] => 08813500
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/813500 | Cache memory with dual-way arrays and multiplexed parallel output | Mar 6, 1997 | Issued |
Array
(
[id] => 1353111
[patent_doc_number] => 06594728
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Cache memory with dual-way arrays and multiplexed parallel output'
[patent_app_type] => B1
[patent_app_number] => 08/813500
[patent_app_country] => US
[patent_app_date] => 1997-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 14133
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/594/06594728.pdf
[firstpage_image] =>[orig_patent_app_number] => 08813500
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/813500 | Cache memory with dual-way arrays and multiplexed parallel output | Mar 6, 1997 | Issued |
Array
(
[id] => 1353111
[patent_doc_number] => 06594728
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Cache memory with dual-way arrays and multiplexed parallel output'
[patent_app_type] => B1
[patent_app_number] => 08/813500
[patent_app_country] => US
[patent_app_date] => 1997-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 14133
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/594/06594728.pdf
[firstpage_image] =>[orig_patent_app_number] => 08813500
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/813500 | Cache memory with dual-way arrays and multiplexed parallel output | Mar 6, 1997 | Issued |
Array
(
[id] => 4192667
[patent_doc_number] => 06141740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Apparatus and method for microcode patching for generating a next address'
[patent_app_type] => 1
[patent_app_number] => 8/808483
[patent_app_country] => US
[patent_app_date] => 1997-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 15605
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141740.pdf
[firstpage_image] =>[orig_patent_app_number] => 808483
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/808483 | Apparatus and method for microcode patching for generating a next address | Mar 2, 1997 | Issued |
Array
(
[id] => 4209053
[patent_doc_number] => 06154826
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order'
[patent_app_type] => 1
[patent_app_number] => 8/808355
[patent_app_country] => US
[patent_app_date] => 1997-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 65
[patent_figures_cnt] => 65
[patent_no_of_words] => 18424
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/154/06154826.pdf
[firstpage_image] =>[orig_patent_app_number] => 808355
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/808355 | Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order | Feb 27, 1997 | Issued |