Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4254984 [patent_doc_number] => 06119201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Disk under-run protection using formatted padding sectors' [patent_app_type] => 1 [patent_app_number] => 8/801337 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2773 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119201.pdf [firstpage_image] =>[orig_patent_app_number] => 801337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801337
Disk under-run protection using formatted padding sectors Feb 18, 1997 Issued
Array ( [id] => 3978293 [patent_doc_number] => 05937434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method of managing a symmetrically blocked nonvolatile memory having a bifurcated storage architecture' [patent_app_type] => 1 [patent_app_number] => 8/801781 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12242 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937434.pdf [firstpage_image] =>[orig_patent_app_number] => 801781 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801781
Method of managing a symmetrically blocked nonvolatile memory having a bifurcated storage architecture Feb 13, 1997 Issued
Array ( [id] => 1001815 [patent_doc_number] => 06912680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Memory system with dynamic timing correction' [patent_app_type] => utility [patent_app_number] => 08/798227 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3072 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912680.pdf [firstpage_image] =>[orig_patent_app_number] => 08798227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798227
Memory system with dynamic timing correction Feb 10, 1997 Issued
Array ( [id] => 6973988 [patent_doc_number] => 20010003838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-14 [patent_title] => 'WRITE PURGE PARTIAL IN SCI BASED SYSTEM' [patent_app_type] => new-utility [patent_app_number] => 08/792077 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2148 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003838.pdf [firstpage_image] =>[orig_patent_app_number] => 08792077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792077
Sharing list for multi-node DMA write operations Jan 30, 1997 Issued
Array ( [id] => 3798574 [patent_doc_number] => 05809557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Memory array comprised of multiple FIFO devices' [patent_app_type] => 1 [patent_app_number] => 8/790153 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2197 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809557.pdf [firstpage_image] =>[orig_patent_app_number] => 790153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790153
Memory array comprised of multiple FIFO devices Jan 27, 1997 Issued
Array ( [id] => 3989957 [patent_doc_number] => 05905909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Memory device having circuitry for initializing and reprogramming a control operation feature' [patent_app_type] => 1 [patent_app_number] => 8/783379 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7149 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905909.pdf [firstpage_image] =>[orig_patent_app_number] => 783379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783379
Memory device having circuitry for initializing and reprogramming a control operation feature Jan 12, 1997 Issued
Array ( [id] => 3830524 [patent_doc_number] => 05812842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method for initializing and reprogramming a control operation feature of a memory device' [patent_app_type] => 1 [patent_app_number] => 8/783381 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6989 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812842.pdf [firstpage_image] =>[orig_patent_app_number] => 783381 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783381
Method for initializing and reprogramming a control operation feature of a memory device Jan 12, 1997 Issued
Array ( [id] => 3960437 [patent_doc_number] => 05930830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'System and method for concatenating discontiguous memory pages' [patent_app_type] => 1 [patent_app_number] => 8/783599 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5917 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930830.pdf [firstpage_image] =>[orig_patent_app_number] => 783599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783599
System and method for concatenating discontiguous memory pages Jan 12, 1997 Issued
Array ( [id] => 3805814 [patent_doc_number] => 05822766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Main memory interface for high speed data transfer' [patent_app_type] => 1 [patent_app_number] => 8/780965 [patent_app_country] => US [patent_app_date] => 1997-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3848 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822766.pdf [firstpage_image] =>[orig_patent_app_number] => 780965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780965
Main memory interface for high speed data transfer Jan 8, 1997 Issued
Array ( [id] => 3898001 [patent_doc_number] => 05765188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Memory presence and type detection using multiplexed memory select line' [patent_app_type] => 1 [patent_app_number] => 8/780303 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8562 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765188.pdf [firstpage_image] =>[orig_patent_app_number] => 780303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780303
Memory presence and type detection using multiplexed memory select line Jan 7, 1997 Issued
Array ( [id] => 4155934 [patent_doc_number] => 06122711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method of and apparatus for store-in second level cache flush' [patent_app_type] => 1 [patent_app_number] => 8/779472 [patent_app_country] => US [patent_app_date] => 1997-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5217 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122711.pdf [firstpage_image] =>[orig_patent_app_number] => 779472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779472
Method of and apparatus for store-in second level cache flush Jan 6, 1997 Issued
Array ( [id] => 4059802 [patent_doc_number] => 05875479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and means for making a dual volume level copy in a DASD storage subsystem subject to updating during the copy interval' [patent_app_type] => 1 [patent_app_number] => 8/779577 [patent_app_country] => US [patent_app_date] => 1997-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4709 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875479.pdf [firstpage_image] =>[orig_patent_app_number] => 779577 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779577
Method and means for making a dual volume level copy in a DASD storage subsystem subject to updating during the copy interval Jan 6, 1997 Issued
Array ( [id] => 4144696 [patent_doc_number] => 06034919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method and apparatus for using extended-data output memory devices in a system designed for fast page mode memory devices' [patent_app_type] => 1 [patent_app_number] => 8/775315 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034919.pdf [firstpage_image] =>[orig_patent_app_number] => 775315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775315
Method and apparatus for using extended-data output memory devices in a system designed for fast page mode memory devices Dec 30, 1996 Issued
Array ( [id] => 4290311 [patent_doc_number] => 06308248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method and system for allocating memory space using mapping controller, page table and frame numbers' [patent_app_type] => 1 [patent_app_number] => 8/777781 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4657 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308248.pdf [firstpage_image] =>[orig_patent_app_number] => 777781 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777781
Method and system for allocating memory space using mapping controller, page table and frame numbers Dec 30, 1996 Issued
Array ( [id] => 3913111 [patent_doc_number] => 05835931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Arrangement for determining the configuration of a memory utilizing dedicated control devices and dedicated control lines' [patent_app_type] => 1 [patent_app_number] => 8/775465 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835931.pdf [firstpage_image] =>[orig_patent_app_number] => 775465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775465
Arrangement for determining the configuration of a memory utilizing dedicated control devices and dedicated control lines Dec 29, 1996 Issued
Array ( [id] => 3853485 [patent_doc_number] => 05761728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Asynchronous access system controlling processing modules making requests to a shared system memory' [patent_app_type] => 1 [patent_app_number] => 8/777184 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6958 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761728.pdf [firstpage_image] =>[orig_patent_app_number] => 777184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777184
Asynchronous access system controlling processing modules making requests to a shared system memory Dec 26, 1996 Issued
08/772645 CONDITIONAL RESTORE FOR SRAM Dec 22, 1996 Abandoned
Array ( [id] => 4236439 [patent_doc_number] => 06041390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Token mechanism for cache-line replacement within a cache memory having redundant cache lines' [patent_app_type] => 1 [patent_app_number] => 8/773545 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2812 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041390.pdf [firstpage_image] =>[orig_patent_app_number] => 773545 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773545
Token mechanism for cache-line replacement within a cache memory having redundant cache lines Dec 22, 1996 Issued
Array ( [id] => 4060896 [patent_doc_number] => 05895486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and system for selectively invalidating cache lines during multiple word store operations for memory coherence' [patent_app_type] => 1 [patent_app_number] => 8/770997 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8843 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895486.pdf [firstpage_image] =>[orig_patent_app_number] => 770997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770997
Method and system for selectively invalidating cache lines during multiple word store operations for memory coherence Dec 19, 1996 Issued
Array ( [id] => 4058929 [patent_doc_number] => 05909691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Method for developing physical disk drive specific commands from logical disk access commands for use in a disk array' [patent_app_type] => 1 [patent_app_number] => 8/777679 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 23375 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909691.pdf [firstpage_image] =>[orig_patent_app_number] => 777679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777679
Method for developing physical disk drive specific commands from logical disk access commands for use in a disk array Dec 19, 1996 Issued
Menu