Troy Chambers

Array ( [id] => 3670525 [patent_doc_number] => 05627946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Hard disk format using frames of sectors to optimize location of servo bursts' [patent_app_type] => 1 [patent_app_number] => 8/636296 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 43 [patent_no_of_words] => 11045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627946.pdf [firstpage_image] =>[orig_patent_app_number] => 636296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3823886 [patent_doc_number] => 05832088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Method and apparatus for preventing data copying from a disk using data lengths too large for a pirate medium' [patent_app_type] => 1 [patent_app_number] => 8/624391 [patent_app_country] => US [patent_app_date] => 1996-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 27833 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832088.pdf [firstpage_image] =>[orig_patent_app_number] => 624391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758586 [patent_doc_number] => 05754821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Method and system for providing access to a protected partition of a memory device utilizing a passthru command' [patent_app_type] => 1 [patent_app_number] => 8/622229 [patent_app_country] => US [patent_app_date] => 1996-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3973 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754821.pdf [firstpage_image] =>[orig_patent_app_number] => 622229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3841705 [patent_doc_number] => 05784590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Slave cache having sub-line valid bits updated by a master cache' [patent_app_type] => 1 [patent_app_number] => 8/618637 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10769 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784590.pdf [firstpage_image] =>[orig_patent_app_number] => 618637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4059591 [patent_doc_number] => 05875464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Computer system with private and shared partitions in cache' [patent_app_type] => 1 [patent_app_number] => 8/617347 [patent_app_country] => US [patent_app_date] => 1996-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 15107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875464.pdf [firstpage_image] =>[orig_patent_app_number] => 617347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805940 [patent_doc_number] => 05822776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Multiplexed random access memory with time division multiplexing through a single read/write port' [patent_app_type] => 1 [patent_app_number] => 8/613519 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2602 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822776.pdf [firstpage_image] =>[orig_patent_app_number] => 613519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3860259 [patent_doc_number] => 05848436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method and apparatus for efficiently providing data from a data storage medium to a processing entity' [patent_app_type] => 1 [patent_app_number] => 8/612631 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4261 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848436.pdf [firstpage_image] =>[orig_patent_app_number] => 612631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805780 [patent_doc_number] => 05822764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and circuit for efficiently replacing invalid locked portions of a cache with valid data' [patent_app_type] => 1 [patent_app_number] => 8/610013 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2597 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822764.pdf [firstpage_image] =>[orig_patent_app_number] => 610013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3663036 [patent_doc_number] => 05685010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Data transfer control device for controlling data transfer between shared memories of network clusters' [patent_app_type] => 1 [patent_app_number] => 8/603839 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5670 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/685/05685010.pdf [firstpage_image] =>[orig_patent_app_number] => 603839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3775438 [patent_doc_number] => 05742755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Error-handling circuit and method for memory address alignment double fault' [patent_app_type] => 1 [patent_app_number] => 8/603999 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742755.pdf [firstpage_image] =>[orig_patent_app_number] => 603999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3521795 [patent_doc_number] => 05588138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Dynamic partitioning of memory into central and peripheral subregions' [patent_app_type] => 1 [patent_app_number] => 8/598401 [patent_app_country] => US [patent_app_date] => 1996-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 10081 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588138.pdf [firstpage_image] =>[orig_patent_app_number] => 598401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767239 [patent_doc_number] => 05721863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address' [patent_app_type] => 1 [patent_app_number] => 8/593639 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5849 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721863.pdf [firstpage_image] =>[orig_patent_app_number] => 593639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3804241 [patent_doc_number] => 05737636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method and system for detecting bypass errors in a load/store unit of a superscalar processor' [patent_app_type] => 1 [patent_app_number] => 8/591249 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3746 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737636.pdf [firstpage_image] =>[orig_patent_app_number] => 591249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3637440 [patent_doc_number] => 05603061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Method for prioritizing memory access requests using a selected priority code' [patent_app_type] => 1 [patent_app_number] => 8/587132 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603061.pdf [firstpage_image] =>[orig_patent_app_number] => 587132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3675568 [patent_doc_number] => 05625796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Method and apparatus for concurrently accessing multiple memories with different timing requirements' [patent_app_type] => 1 [patent_app_number] => 8/584725 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3943 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625796.pdf [firstpage_image] =>[orig_patent_app_number] => 584725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3778104 [patent_doc_number] => 05742935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Method and apparatus for controlling the protection mode of flash memory' [patent_app_type] => 1 [patent_app_number] => 8/581049 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3246 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742935.pdf [firstpage_image] =>[orig_patent_app_number] => 581049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3644053 [patent_doc_number] => 05631871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle' [patent_app_type] => 1 [patent_app_number] => 8/578151 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 72 [patent_no_of_words] => 30906 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631871.pdf [firstpage_image] =>[orig_patent_app_number] => 578151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3765839 [patent_doc_number] => 05802596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'High speed synchronous DRAM having a pipeline structure' [patent_app_type] => 1 [patent_app_number] => 8/570549 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 4899 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802596.pdf [firstpage_image] =>[orig_patent_app_number] => 570549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3798331 [patent_doc_number] => 05809540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Processor command for prompting a storage controller to write a day clock value to specified memory location' [patent_app_type] => 1 [patent_app_number] => 8/577909 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3156 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809540.pdf [firstpage_image] =>[orig_patent_app_number] => 577909 [rel_patent_id] =>[rel_patent_doc_number] =>)