Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
08/566719 SYNCHRONOUS SRAM HAVING PIPELINED ENABLE Dec 3, 1995 Abandoned
Array ( [id] => 3760708 [patent_doc_number] => 05717901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Variable depth and width memory device' [patent_app_type] => 1 [patent_app_number] => 8/555109 [patent_app_country] => US [patent_app_date] => 1995-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3659 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717901.pdf [firstpage_image] =>[orig_patent_app_number] => 555109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/555109
Variable depth and width memory device Nov 7, 1995 Issued
Array ( [id] => 4057919 [patent_doc_number] => 05875352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and apparatus for multiple channel direct memory access control' [patent_app_type] => 1 [patent_app_number] => 8/553041 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875352.pdf [firstpage_image] =>[orig_patent_app_number] => 553041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/553041
Method and apparatus for multiple channel direct memory access control Nov 2, 1995 Issued
Array ( [id] => 3755436 [patent_doc_number] => 05787252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Filtering system and method for high performance network management map' [patent_app_type] => 1 [patent_app_number] => 8/551499 [patent_app_country] => US [patent_app_date] => 1995-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11439 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787252.pdf [firstpage_image] =>[orig_patent_app_number] => 551499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551499
Filtering system and method for high performance network management map Oct 31, 1995 Issued
Array ( [id] => 3674482 [patent_doc_number] => 05657469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Selective access to divided word line segments in cache memory' [patent_app_type] => 1 [patent_app_number] => 8/549073 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4960 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657469.pdf [firstpage_image] =>[orig_patent_app_number] => 549073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/549073
Selective access to divided word line segments in cache memory Oct 26, 1995 Issued
Array ( [id] => 3806026 [patent_doc_number] => 05822782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Methods and structure to maintain raid configuration information on disks of the array' [patent_app_type] => 1 [patent_app_number] => 8/549383 [patent_app_country] => US [patent_app_date] => 1995-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6080 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822782.pdf [firstpage_image] =>[orig_patent_app_number] => 549383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/549383
Methods and structure to maintain raid configuration information on disks of the array Oct 26, 1995 Issued
Array ( [id] => 1415062 [patent_doc_number] => 06549948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Variable frame rate adjustment in a video system' [patent_app_type] => B1 [patent_app_number] => 08/544153 [patent_app_country] => US [patent_app_date] => 1995-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 10361 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549948.pdf [firstpage_image] =>[orig_patent_app_number] => 08544153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544153
Variable frame rate adjustment in a video system Oct 16, 1995 Issued
Array ( [id] => 4204014 [patent_doc_number] => 06161192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Raid array data storage system with storage device consistency bits and raidset consistency bits' [patent_app_type] => 1 [patent_app_number] => 8/542827 [patent_app_country] => US [patent_app_date] => 1995-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161192.pdf [firstpage_image] =>[orig_patent_app_number] => 542827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542827
Raid array data storage system with storage device consistency bits and raidset consistency bits Oct 12, 1995 Issued
Array ( [id] => 3853217 [patent_doc_number] => 05761710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Information apparatus with cache memory for data and data management information' [patent_app_type] => 1 [patent_app_number] => 8/539849 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6107 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761710.pdf [firstpage_image] =>[orig_patent_app_number] => 539849 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539849
Information apparatus with cache memory for data and data management information Oct 5, 1995 Issued
Array ( [id] => 4057390 [patent_doc_number] => 05913028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Client/server data traffic delivery system and method' [patent_app_type] => 1 [patent_app_number] => 8/540589 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9618 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913028.pdf [firstpage_image] =>[orig_patent_app_number] => 540589 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540589
Client/server data traffic delivery system and method Oct 5, 1995 Issued
Array ( [id] => 4029697 [patent_doc_number] => 05907672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'System for backing up computer disk volumes with error remapping of flawed memory addresses' [patent_app_type] => 1 [patent_app_number] => 8/539315 [patent_app_country] => US [patent_app_date] => 1995-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10904 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907672.pdf [firstpage_image] =>[orig_patent_app_number] => 539315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539315
System for backing up computer disk volumes with error remapping of flawed memory addresses Oct 3, 1995 Issued
Array ( [id] => 3898305 [patent_doc_number] => 05765208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method of speculatively executing store instructions prior to performing snoop operations' [patent_app_type] => 1 [patent_app_number] => 8/537049 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3058 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765208.pdf [firstpage_image] =>[orig_patent_app_number] => 537049 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537049
Method of speculatively executing store instructions prior to performing snoop operations Sep 28, 1995 Issued
Array ( [id] => 3756385 [patent_doc_number] => 05787311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Integrated circuit multiport memory having serial access bit mask register and method for writing in the multiport memory' [patent_app_type] => 1 [patent_app_number] => 8/528181 [patent_app_country] => US [patent_app_date] => 1995-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787311.pdf [firstpage_image] =>[orig_patent_app_number] => 528181 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/528181
Integrated circuit multiport memory having serial access bit mask register and method for writing in the multiport memory Sep 13, 1995 Issued
Array ( [id] => 4019639 [patent_doc_number] => 05860104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates' [patent_app_type] => 1 [patent_app_number] => 8/521627 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 68 [patent_no_of_words] => 104850 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860104.pdf [firstpage_image] =>[orig_patent_app_number] => 521627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521627
Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates Aug 30, 1995 Issued
Array ( [id] => 3908388 [patent_doc_number] => 05778439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Programmable logic device with hierarchical confiquration and state storage' [patent_app_type] => 1 [patent_app_number] => 8/517019 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 81 [patent_no_of_words] => 25648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778439.pdf [firstpage_image] =>[orig_patent_app_number] => 517019 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517019
Programmable logic device with hierarchical confiquration and state storage Aug 17, 1995 Issued
Array ( [id] => 3569265 [patent_doc_number] => 05502836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method for disk restriping during system operation' [patent_app_type] => 1 [patent_app_number] => 8/504144 [patent_app_country] => US [patent_app_date] => 1995-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9116 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502836.pdf [firstpage_image] =>[orig_patent_app_number] => 504144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/504144
Method for disk restriping during system operation Jul 18, 1995 Issued
08/474739 COMPUTING DEVICE MEMORY SYSTEM Jun 6, 1995 Abandoned
Array ( [id] => 4225714 [patent_doc_number] => 06029224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Self-contained memory apparatus having diverse types of memory and distributed control' [patent_app_type] => 1 [patent_app_number] => 8/477175 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029224.pdf [firstpage_image] =>[orig_patent_app_number] => 477175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477175
Self-contained memory apparatus having diverse types of memory and distributed control Jun 6, 1995 Issued
Array ( [id] => 3803003 [patent_doc_number] => 05737564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops' [patent_app_type] => 1 [patent_app_number] => 8/463271 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2099 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737564.pdf [firstpage_image] =>[orig_patent_app_number] => 463271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/463271
Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops Jun 4, 1995 Issued
Array ( [id] => 3922815 [patent_doc_number] => 05752263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads' [patent_app_type] => 1 [patent_app_number] => 8/464351 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4844 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752263.pdf [firstpage_image] =>[orig_patent_app_number] => 464351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/464351
Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads Jun 4, 1995 Issued
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