Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3900907 [patent_doc_number] => 05749091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Cache controller with index stack for coherency fault tolerance' [patent_app_type] => 1 [patent_app_number] => 8/355093 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9896 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749091.pdf [firstpage_image] =>[orig_patent_app_number] => 355093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355093
Cache controller with index stack for coherency fault tolerance Dec 12, 1994 Issued
Array ( [id] => 3694461 [patent_doc_number] => 05634030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Semiconductor memory device for incrementing address at high speed in burst access' [patent_app_type] => 1 [patent_app_number] => 8/357255 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4224 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634030.pdf [firstpage_image] =>[orig_patent_app_number] => 357255 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357255
Semiconductor memory device for incrementing address at high speed in burst access Dec 12, 1994 Issued
Array ( [id] => 3707717 [patent_doc_number] => 05680574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Data distribution utilizing a master disk unit for fetching and for writing to remaining disk units' [patent_app_type] => 1 [patent_app_number] => 8/355274 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 14586 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680574.pdf [firstpage_image] =>[orig_patent_app_number] => 355274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355274
Data distribution utilizing a master disk unit for fetching and for writing to remaining disk units Dec 11, 1994 Issued
Array ( [id] => 3701028 [patent_doc_number] => 05644752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Combined store queue for a master-slave cache system' [patent_app_type] => 1 [patent_app_number] => 8/350815 [patent_app_country] => US [patent_app_date] => 1994-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10043 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644752.pdf [firstpage_image] =>[orig_patent_app_number] => 350815 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/350815
Combined store queue for a master-slave cache system Dec 6, 1994 Issued
08/350720 MEMORY ACCESS SYSTEM WITH OVERWRITE PREVENTION FOR OVERLAPPING WRITES Dec 6, 1994 Abandoned
Array ( [id] => 3503791 [patent_doc_number] => 05561815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'System and method for control of coexisting code and image data in memory' [patent_app_type] => 1 [patent_app_number] => 8/341282 [patent_app_country] => US [patent_app_date] => 1994-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8981 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561815.pdf [firstpage_image] =>[orig_patent_app_number] => 341282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341282
System and method for control of coexisting code and image data in memory Nov 15, 1994 Issued
Array ( [id] => 3674388 [patent_doc_number] => 05649231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Storage control method and apparatus having a buffer storage for transferring variable amounts of data to a main storage based on current system load' [patent_app_type] => 1 [patent_app_number] => 8/327848 [patent_app_country] => US [patent_app_date] => 1994-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6799 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649231.pdf [firstpage_image] =>[orig_patent_app_number] => 327848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/327848
Storage control method and apparatus having a buffer storage for transferring variable amounts of data to a main storage based on current system load Oct 20, 1994 Issued
08/324124 CACHE MEMORY WITH DUAL-WHY ARRAYS AND MULTIPLEXED PARALLEL OUTPUT Oct 13, 1994 Abandoned
Array ( [id] => 3122757 [patent_doc_number] => 05465349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'System for monitoring abnormal integrated circuit operating conditions and causing selective microprocessor interrupts' [patent_app_type] => 1 [patent_app_number] => 8/384531 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1968 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465349.pdf [firstpage_image] =>[orig_patent_app_number] => 384531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/384531
System for monitoring abnormal integrated circuit operating conditions and causing selective microprocessor interrupts Oct 4, 1994 Issued
Array ( [id] => 3897453 [patent_doc_number] => 05805855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Data cache array having multiple content addressable fields per cache line' [patent_app_type] => 1 [patent_app_number] => 8/319329 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7667 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805855.pdf [firstpage_image] =>[orig_patent_app_number] => 319329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/319329
Data cache array having multiple content addressable fields per cache line Oct 4, 1994 Issued
Array ( [id] => 4411869 [patent_doc_number] => 06298388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Electronic apparatus and method for discriminating whether a first or second card is attached thereto' [patent_app_type] => 1 [patent_app_number] => 8/307494 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3562 [patent_no_of_claims] => 224 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298388.pdf [firstpage_image] =>[orig_patent_app_number] => 307494 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/307494
Electronic apparatus and method for discriminating whether a first or second card is attached thereto Sep 15, 1994 Issued
Array ( [id] => 3595851 [patent_doc_number] => 05581737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method and apparatus for expansion, contraction, and reapportionment of structured external storage structures' [patent_app_type] => 1 [patent_app_number] => 8/304458 [patent_app_country] => US [patent_app_date] => 1994-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 24628 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581737.pdf [firstpage_image] =>[orig_patent_app_number] => 304458 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/304458
Method and apparatus for expansion, contraction, and reapportionment of structured external storage structures Sep 11, 1994 Issued
Array ( [id] => 3702278 [patent_doc_number] => 05604917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'IC memory card having masking function for preventing writing of data into a fixed memory area' [patent_app_type] => 1 [patent_app_number] => 8/294870 [patent_app_country] => US [patent_app_date] => 1994-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3220 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604917.pdf [firstpage_image] =>[orig_patent_app_number] => 294870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/294870
IC memory card having masking function for preventing writing of data into a fixed memory area Aug 28, 1994 Issued
Array ( [id] => 3616651 [patent_doc_number] => 05579508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Main memory managing method and apparatus in which main memory is partitioned into three distinct areas' [patent_app_type] => 1 [patent_app_number] => 8/293334 [patent_app_country] => US [patent_app_date] => 1994-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2698 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579508.pdf [firstpage_image] =>[orig_patent_app_number] => 293334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293334
Main memory managing method and apparatus in which main memory is partitioned into three distinct areas Aug 23, 1994 Issued
08/291179 MULTIPROCESSOR SYSTEM HAVING SHARED MEMORY DIVIDED INTO A PLURALITY OF BANKS Aug 15, 1994 Abandoned
Array ( [id] => 3908070 [patent_doc_number] => 05778418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Mass computer storage system having both solid state and rotating disk types of memory' [patent_app_type] => 1 [patent_app_number] => 8/287107 [patent_app_country] => US [patent_app_date] => 1994-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4238 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778418.pdf [firstpage_image] =>[orig_patent_app_number] => 287107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287107
Mass computer storage system having both solid state and rotating disk types of memory Aug 7, 1994 Issued
Array ( [id] => 3636246 [patent_doc_number] => 05602984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Low thrash cache with selectable tile geometry' [patent_app_type] => 1 [patent_app_number] => 8/284879 [patent_app_country] => US [patent_app_date] => 1994-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6874 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602984.pdf [firstpage_image] =>[orig_patent_app_number] => 284879 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/284879
Low thrash cache with selectable tile geometry Aug 1, 1994 Issued
Array ( [id] => 3671280 [patent_doc_number] => 05627994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Method for the assignment of request streams to cache memories' [patent_app_type] => 1 [patent_app_number] => 8/283098 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12956 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627994.pdf [firstpage_image] =>[orig_patent_app_number] => 283098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283098
Method for the assignment of request streams to cache memories Jul 28, 1994 Issued
Array ( [id] => 3626486 [patent_doc_number] => 05566371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Semiconductor memory device capable of data transfer between memory arrays coupled to different data pins and operating method thereof' [patent_app_type] => 1 [patent_app_number] => 8/282763 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8495 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566371.pdf [firstpage_image] =>[orig_patent_app_number] => 282763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282763
Semiconductor memory device capable of data transfer between memory arrays coupled to different data pins and operating method thereof Jul 28, 1994 Issued
Array ( [id] => 3672731 [patent_doc_number] => 05592649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'RAM control method and apparatus for presetting RAM access modes' [patent_app_type] => 1 [patent_app_number] => 8/279843 [patent_app_country] => US [patent_app_date] => 1994-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 6410 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592649.pdf [firstpage_image] =>[orig_patent_app_number] => 279843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279843
RAM control method and apparatus for presetting RAM access modes Jul 25, 1994 Issued
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