| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Cache controller with index stack for coherency fault tolerance'
[patent_app_type] => 1
[patent_app_number] => 8/355093
[patent_app_country] => US
[patent_app_date] => 1994-12-13
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[patent_doc_number] => 05634030
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Semiconductor memory device for incrementing address at high speed in burst access'
[patent_app_type] => 1
[patent_app_number] => 8/357255
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[patent_app_date] => 1994-12-13
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[firstpage_image] =>[orig_patent_app_number] => 357255
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/357255 | Semiconductor memory device for incrementing address at high speed in burst access | Dec 12, 1994 | Issued |
Array
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[patent_doc_number] => 05680574
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Data distribution utilizing a master disk unit for fetching and for writing to remaining disk units'
[patent_app_type] => 1
[patent_app_number] => 8/355274
[patent_app_country] => US
[patent_app_date] => 1994-12-12
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[firstpage_image] =>[orig_patent_app_number] => 355274
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Array
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[id] => 3701028
[patent_doc_number] => 05644752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Combined store queue for a master-slave cache system'
[patent_app_type] => 1
[patent_app_number] => 8/350815
[patent_app_country] => US
[patent_app_date] => 1994-12-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/350815 | Combined store queue for a master-slave cache system | Dec 6, 1994 | Issued |
| 08/350720 | MEMORY ACCESS SYSTEM WITH OVERWRITE PREVENTION FOR OVERLAPPING WRITES | Dec 6, 1994 | Abandoned |
Array
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[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'System and method for control of coexisting code and image data in memory'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/341282 | System and method for control of coexisting code and image data in memory | Nov 15, 1994 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1997-07-15
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[patent_app_number] => 8/327848
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/327848 | Storage control method and apparatus having a buffer storage for transferring variable amounts of data to a main storage based on current system load | Oct 20, 1994 | Issued |
| 08/324124 | CACHE MEMORY WITH DUAL-WHY ARRAYS AND MULTIPLEXED PARALLEL OUTPUT | Oct 13, 1994 | Abandoned |
Array
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[patent_kind] => NA
[patent_issue_date] => 1995-11-07
[patent_title] => 'System for monitoring abnormal integrated circuit operating conditions and causing selective microprocessor interrupts'
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[patent_app_number] => 8/384531
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Array
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[patent_doc_number] => 05805855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Data cache array having multiple content addressable fields per cache line'
[patent_app_type] => 1
[patent_app_number] => 8/319329
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[patent_app_date] => 1994-10-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319329 | Data cache array having multiple content addressable fields per cache line | Oct 4, 1994 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Electronic apparatus and method for discriminating whether a first or second card is attached thereto'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/307494 | Electronic apparatus and method for discriminating whether a first or second card is attached thereto | Sep 15, 1994 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Method and apparatus for expansion, contraction, and reapportionment of structured external storage structures'
[patent_app_type] => 1
[patent_app_number] => 8/304458
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Array
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[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'IC memory card having masking function for preventing writing of data into a fixed memory area'
[patent_app_type] => 1
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Array
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[id] => 3616651
[patent_doc_number] => 05579508
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[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Main memory managing method and apparatus in which main memory is partitioned into three distinct areas'
[patent_app_type] => 1
[patent_app_number] => 8/293334
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[patent_app_date] => 1994-08-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/293334 | Main memory managing method and apparatus in which main memory is partitioned into three distinct areas | Aug 23, 1994 | Issued |
| 08/291179 | MULTIPROCESSOR SYSTEM HAVING SHARED MEMORY DIVIDED INTO A PLURALITY OF BANKS | Aug 15, 1994 | Abandoned |
Array
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Array
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/283098 | Method for the assignment of request streams to cache memories | Jul 28, 1994 | Issued |
Array
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[patent_kind] => NA
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