Search

Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3776588 [patent_doc_number] => 05742831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Methods and apparatus for maintaining cache coherency during copendency of load and store operations' [patent_app_type] => 1 [patent_app_number] => 8/268338 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3209 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742831.pdf [firstpage_image] =>[orig_patent_app_number] => 268338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/268338
Methods and apparatus for maintaining cache coherency during copendency of load and store operations Jun 29, 1994 Issued
Array ( [id] => 3601090 [patent_doc_number] => 05551001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Master-slave cache system for instruction and data cache memories' [patent_app_type] => 1 [patent_app_number] => 8/267658 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11510 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551001.pdf [firstpage_image] =>[orig_patent_app_number] => 267658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/267658
Master-slave cache system for instruction and data cache memories Jun 28, 1994 Issued
Array ( [id] => 3585958 [patent_doc_number] => 05539919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Microcomputer having function to specify functional block having data to be monitored and to output data as an anaglog signal' [patent_app_type] => 1 [patent_app_number] => 8/265556 [patent_app_country] => US [patent_app_date] => 1994-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2788 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539919.pdf [firstpage_image] =>[orig_patent_app_number] => 265556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/265556
Microcomputer having function to specify functional block having data to be monitored and to output data as an anaglog signal Jun 23, 1994 Issued
Array ( [id] => 3432422 [patent_doc_number] => 05479632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Microcomputer having two-level memory to facilitate calculation of effective addresses' [patent_app_type] => 1 [patent_app_number] => 8/248833 [patent_app_country] => US [patent_app_date] => 1994-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2786 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479632.pdf [firstpage_image] =>[orig_patent_app_number] => 248833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/248833
Microcomputer having two-level memory to facilitate calculation of effective addresses May 24, 1994 Issued
Array ( [id] => 3677700 [patent_doc_number] => 05668974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Memory with variable levels of interleaving and associated configurator circuit' [patent_app_type] => 1 [patent_app_number] => 8/247548 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7353 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668974.pdf [firstpage_image] =>[orig_patent_app_number] => 247548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247548
Memory with variable levels of interleaving and associated configurator circuit May 22, 1994 Issued
08/242684 METHOD AND APPARATUS FOR CONCURRENTLY ACCESSING A MULTIPLE MEMORIES May 11, 1994 Abandoned
08/238248 REMOVABLE PROCESSOR BOARD HAVING FIRST, SECOND AND THIRD LEVEL CACHE SYSTEMS FOR USE IN A MULTIPROCESSOR COMPUTER SYSTEM May 3, 1994 Abandoned
Array ( [id] => 3566582 [patent_doc_number] => 05519853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method and apparatus for enhancing synchronous I/O in a computer system with a non-volatile memory and using an acceleration device driver in a computer operating system' [patent_app_type] => 1 [patent_app_number] => 8/235755 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519853.pdf [firstpage_image] =>[orig_patent_app_number] => 235755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/235755
Method and apparatus for enhancing synchronous I/O in a computer system with a non-volatile memory and using an acceleration device driver in a computer operating system Apr 28, 1994 Issued
Array ( [id] => 4076696 [patent_doc_number] => 05896551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Initializing and reprogramming circuitry for state independent memory array burst operations control' [patent_app_type] => 1 [patent_app_number] => 8/228051 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7120 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896551.pdf [firstpage_image] =>[orig_patent_app_number] => 228051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228051
Initializing and reprogramming circuitry for state independent memory array burst operations control Apr 14, 1994 Issued
Array ( [id] => 3558063 [patent_doc_number] => 05546343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method and apparatus for a single instruction operating multiple processors on a memory chip' [patent_app_type] => 1 [patent_app_number] => 8/224998 [patent_app_country] => US [patent_app_date] => 1994-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6818 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546343.pdf [firstpage_image] =>[orig_patent_app_number] => 224998 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/224998
Method and apparatus for a single instruction operating multiple processors on a memory chip Apr 6, 1994 Issued
Array ( [id] => 3506706 [patent_doc_number] => 05537635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Method and system for assignment of reclaim vectors in a partitioned cache with a virtual minimum partition size' [patent_app_type] => 1 [patent_app_number] => 8/222219 [patent_app_country] => US [patent_app_date] => 1994-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4680 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537635.pdf [firstpage_image] =>[orig_patent_app_number] => 222219 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/222219
Method and system for assignment of reclaim vectors in a partitioned cache with a virtual minimum partition size Apr 3, 1994 Issued
Array ( [id] => 3913498 [patent_doc_number] => 05835957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'System and method for a fast data write from a computer system to a storage system by overlapping transfer operations' [patent_app_type] => 1 [patent_app_number] => 8/222516 [patent_app_country] => US [patent_app_date] => 1994-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2653 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835957.pdf [firstpage_image] =>[orig_patent_app_number] => 222516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/222516
System and method for a fast data write from a computer system to a storage system by overlapping transfer operations Mar 31, 1994 Issued
Array ( [id] => 3603733 [patent_doc_number] => 05586297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Partial cache line write transactions in a computing system with a write back cache' [patent_app_type] => 1 [patent_app_number] => 8/217588 [patent_app_country] => US [patent_app_date] => 1994-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4376 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586297.pdf [firstpage_image] =>[orig_patent_app_number] => 217588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/217588
Partial cache line write transactions in a computing system with a write back cache Mar 23, 1994 Issued
Array ( [id] => 3626404 [patent_doc_number] => 05535367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Demultiplexing initialization data to be transferred to memory through a plurality of registers with error detection data' [patent_app_type] => 1 [patent_app_number] => 8/214083 [patent_app_country] => US [patent_app_date] => 1994-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1570 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535367.pdf [firstpage_image] =>[orig_patent_app_number] => 214083 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/214083
Demultiplexing initialization data to be transferred to memory through a plurality of registers with error detection data Mar 15, 1994 Issued
Array ( [id] => 3622395 [patent_doc_number] => 05590379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method and apparatus for cache memory access with separate fetch and store queues' [patent_app_type] => 1 [patent_app_number] => 8/212129 [patent_app_country] => US [patent_app_date] => 1994-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6561 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590379.pdf [firstpage_image] =>[orig_patent_app_number] => 212129 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/212129
Method and apparatus for cache memory access with separate fetch and store queues Mar 13, 1994 Issued
Array ( [id] => 3432379 [patent_doc_number] => 05479629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Method and apparatus for translation request buffer and requestor table for minimizing the number of accesses to the same address' [patent_app_type] => 1 [patent_app_number] => 8/208926 [patent_app_country] => US [patent_app_date] => 1994-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3592 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479629.pdf [firstpage_image] =>[orig_patent_app_number] => 208926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/208926
Method and apparatus for translation request buffer and requestor table for minimizing the number of accesses to the same address Mar 10, 1994 Issued
Array ( [id] => 3667525 [patent_doc_number] => 05623640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Data memory system that exchanges data in data locations with other data locations based on the number of writes to the memory' [patent_app_type] => 1 [patent_app_number] => 8/207153 [patent_app_country] => US [patent_app_date] => 1994-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3025 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623640.pdf [firstpage_image] =>[orig_patent_app_number] => 207153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/207153
Data memory system that exchanges data in data locations with other data locations based on the number of writes to the memory Mar 7, 1994 Issued
Array ( [id] => 3600150 [patent_doc_number] => 05497477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'System and method for replacing a data entry in a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/206245 [patent_app_country] => US [patent_app_date] => 1994-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4906 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497477.pdf [firstpage_image] =>[orig_patent_app_number] => 206245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/206245
System and method for replacing a data entry in a cache memory Mar 6, 1994 Issued
Array ( [id] => 3579512 [patent_doc_number] => 05485593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Data structure access control circuit and method utilizing tag bits indicating address match and memory fullness conditions' [patent_app_type] => 1 [patent_app_number] => 8/205333 [patent_app_country] => US [patent_app_date] => 1994-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3793 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485593.pdf [firstpage_image] =>[orig_patent_app_number] => 205333 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/205333
Data structure access control circuit and method utilizing tag bits indicating address match and memory fullness conditions Mar 2, 1994 Issued
Array ( [id] => 3734579 [patent_doc_number] => 05682516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Computer system that maintains system wide cache coherency during deferred communication transactions' [patent_app_type] => 1 [patent_app_number] => 8/205023 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9794 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682516.pdf [firstpage_image] =>[orig_patent_app_number] => 205023 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/205023
Computer system that maintains system wide cache coherency during deferred communication transactions Feb 28, 1994 Issued
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