Troy Chambers

Array ( [id] => 3647795 [patent_doc_number] => 05611070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Methods and apparatus for performing a write/load cache protocol' [patent_app_type] => 1 [patent_app_number] => 8/149139 [patent_app_country] => US [patent_app_date] => 1993-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5288 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/611/05611070.pdf [firstpage_image] =>[orig_patent_app_number] => 149139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601205 [patent_doc_number] => 05551009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Expandable high performance FIFO design which includes memory cells having respective cell multiplexors' [patent_app_type] => 1 [patent_app_number] => 8/134504 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10580 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551009.pdf [firstpage_image] =>[orig_patent_app_number] => 134504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3585915 [patent_doc_number] => 05539916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'DMA control for continuing transfer to input/output device in a cycle steal mode' [patent_app_type] => 1 [patent_app_number] => 8/116303 [patent_app_country] => US [patent_app_date] => 1993-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2176 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539916.pdf [firstpage_image] =>[orig_patent_app_number] => 116303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3674179 [patent_doc_number] => 05649217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Switching system having control circuit and plural buffer memories for data exchange in asynchronous transfer mode' [patent_app_type] => 1 [patent_app_number] => 8/116215 [patent_app_country] => US [patent_app_date] => 1993-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11520 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649217.pdf [firstpage_image] =>[orig_patent_app_number] => 116215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3454315 [patent_doc_number] => 05430861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Computer using optically encoded virtual memory' [patent_app_type] => 1 [patent_app_number] => 8/104241 [patent_app_country] => US [patent_app_date] => 1993-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6995 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430861.pdf [firstpage_image] =>[orig_patent_app_number] => 104241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3605870 [patent_doc_number] => 05522056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Cache memory with plurality of congruence sets and sense amplifiers shared among the congruence sets' [patent_app_type] => 1 [patent_app_number] => 8/101800 [patent_app_country] => US [patent_app_date] => 1993-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3867 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/522/05522056.pdf [firstpage_image] =>[orig_patent_app_number] => 101800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3460370 [patent_doc_number] => 05386540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Method and apparatus for transferring data within a computer using a burst sequence which includes modified bytes and a minimum number of unmodified bytes' [patent_app_type] => 1 [patent_app_number] => 8/098763 [patent_app_country] => US [patent_app_date] => 1993-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2082 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386540.pdf [firstpage_image] =>[orig_patent_app_number] => 098763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3437954 [patent_doc_number] => 05404487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Disc access control method for cache-embedded disc control apparatus with function-degradation capability of data transmission path' [patent_app_type] => 1 [patent_app_number] => 8/089633 [patent_app_country] => US [patent_app_date] => 1993-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9958 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404487.pdf [firstpage_image] =>[orig_patent_app_number] => 089633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532650 [patent_doc_number] => 05490253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Multiprocessor system using odd/even data buses with a timeshared address bus' [patent_app_type] => 1 [patent_app_number] => 8/080600 [patent_app_country] => US [patent_app_date] => 1993-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4497 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490253.pdf [firstpage_image] =>[orig_patent_app_number] => 080600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3843584 [patent_doc_number] => 05784711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Data cache prefetching under control of instruction cache' [patent_app_type] => 1 [patent_app_number] => 8/080438 [patent_app_country] => US [patent_app_date] => 1993-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4863 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784711.pdf [firstpage_image] =>[orig_patent_app_number] => 080438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3049836 [patent_doc_number] => 05301289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Cache device for supplying a fixed word length of a variable instruction code and instruction fetch device' [patent_app_type] => 1 [patent_app_number] => 8/080048 [patent_app_country] => US [patent_app_date] => 1993-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 11358 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301289.pdf [firstpage_image] =>[orig_patent_app_number] => 080048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3059666 [patent_doc_number] => 05305253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Zero fall-through time asynchronous fifo buffer with nonambiguous empty-full resolution' [patent_app_type] => 1 [patent_app_number] => 8/075846 [patent_app_country] => US [patent_app_date] => 1993-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7341 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/305/05305253.pdf [firstpage_image] =>[orig_patent_app_number] => 075846 [rel_patent_id] =>[rel_patent_doc_number] =>)