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Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316
Applications
StatisticsSubscription-Only

Applications

Application numberTitle of the applicationFiling DateStatus
07/920155 METHOD AND APPARATUS FOR LOAD AND FLAG INSTRUCTION Jul 22, 1992 Abandoned
07/917823 APPARATUS AND METHOD FOR PROVIDING A STALL CACHE Jul 20, 1992 Abandoned
Array ( [id] => 3110401 [patent_doc_number] => 05293598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Random access memory with a plurality of amplifier groups' [patent_app_type] => 1 [patent_app_number] => 7/912135 [patent_app_country] => US [patent_app_date] => 1992-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3017 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293598.pdf [firstpage_image] =>[orig_patent_app_number] => 912135 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/912135 		Random access memory with a plurality of amplifier groups Jul 8, 1992 Issued
Array ( [id] => 3549054 [patent_doc_number] => 05495591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Method and system for cache miss prediction based on previous cache access requests' [patent_app_type] => 1 [patent_app_number] => 7/906618 [patent_app_country] => US [patent_app_date] => 1992-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4633 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495591.pdf [firstpage_image] =>[orig_patent_app_number] => 906618 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/906618 		Method and system for cache miss prediction based on previous cache access requests Jun 29, 1992 Issued
07/905588 FLEXIBLE DISK FORMATS AND DOWN LOAD OF FORMATTER CONTROL STORAGE Jun 25, 1992 Abandoned
Array ( [id] => 3107852 [patent_doc_number] => 05291582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Apparatus for performing direct memory access with stride' [patent_app_type] => 1 [patent_app_number] => 7/874747 [patent_app_country] => US [patent_app_date] => 1992-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3957 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291582.pdf [firstpage_image] =>[orig_patent_app_number] => 874747 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/874747 		Apparatus for performing direct memory access with stride Apr 26, 1992 Issued
Array ( [id] => 3712983 [patent_doc_number] => 05675544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method and apparatus for parallel testing of memory circuits' [patent_app_type] => 1 [patent_app_number] => 7/873523 [patent_app_country] => US [patent_app_date] => 1992-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2315 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675544.pdf [firstpage_image] =>[orig_patent_app_number] => 873523 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/873523 		Method and apparatus for parallel testing of memory circuits Apr 20, 1992 Issued
Array ( [id] => 3029517 [patent_doc_number] => 05303192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Semiconductor memory device having information indicative of presence of defective memory cell' [patent_app_type] => 1 [patent_app_number] => 7/831662 [patent_app_country] => US [patent_app_date] => 1992-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5972 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303192.pdf [firstpage_image] =>[orig_patent_app_number] => 831662 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/831662 		Semiconductor memory device having information indicative of presence of defective memory cell Feb 5, 1992 Issued
07/813378 INTERLEAVED CACHE FOR MULTIPLE ACCESSES PER CLOCK IN A MICROPROCESSOR Dec 22, 1991 Abandoned
07/809667 WRITE OVERLAP WITH OVERWRITE PREVENTION Dec 17, 1991 Abandoned
Array ( [id] => 3012296 [patent_doc_number] => 05359723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only' [patent_app_type] => 1 [patent_app_number] => 7/808108 [patent_app_country] => US [patent_app_date] => 1991-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5134 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359723.pdf [firstpage_image] =>[orig_patent_app_number] => 808108 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/808108 		Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only Dec 15, 1991 Issued
07/805406 COMPUTER SYSTEM HAVING PREDICTABLE CACHE FOR REAL-TIME SYSTEMS Dec 9, 1991 Abandoned
07/803608 ELECTRONIC APPARATUS AND MEHOD FOR DISCRIMINATING WHETHER A FIRST OR SECOND CARD IS ATTACHED THERETO Dec 8, 1991 Abandoned
07/795658 METHOD FOR DISK RESTRIPING DURING SYSTEM OPERATION Nov 20, 1991 Abandoned
07/787246 CACHE CONTROLLER, FAULT TOLERANT COMPUTER AND DATA TRANSFER SYSTEM THEREIN Nov 3, 1991 Abandoned
Array ( [id] => 3016478 [patent_doc_number] => 05375215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank' [patent_app_type] => 1 [patent_app_number] => 7/784546 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6683 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 444 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375215.pdf [firstpage_image] =>[orig_patent_app_number] => 784546 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/784546 		Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank Oct 28, 1991 Issued
07/779817 INTEGRATED CIRCUIT WITH IMPROVED SECURITY OF ACCESS Oct 20, 1991 Abandoned
Array ( [id] => 4060947 [patent_doc_number] => 05895489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Memory management system including an inclusion bit for maintaining cache coherency' [patent_app_type] => 1 [patent_app_number] => 7/777608 [patent_app_country] => US [patent_app_date] => 1991-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3235 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895489.pdf [firstpage_image] =>[orig_patent_app_number] => 777608 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/777608 		Memory management system including an inclusion bit for maintaining cache coherency Oct 15, 1991 Issued
07/778298 EXPANDABLE HIGH PERFORMANCE FIFO DESIGN WHICH INCLUDES CELLS HAVING RESPECTIVE CELL MULTIPLEXORS Oct 14, 1991 Abandoned
07/769316 INFORMATION STORING METHOD AND SYSTEM FOR STORAGE MEDIUM Sep 30, 1991 Abandoned
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