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Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3078059 [patent_doc_number] => 05295254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Semiconductor memory device cell array divided into a plurality of blocks' [patent_app_type] => 1 [patent_app_number] => 7/767898 [patent_app_country] => US [patent_app_date] => 1991-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3867 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295254.pdf [firstpage_image] =>[orig_patent_app_number] => 767898 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/767898
Semiconductor memory device cell array divided into a plurality of blocks Sep 29, 1991 Issued
07/767106 MASS COMPUTER STORAGE SYSTEM HAVING BOTH SOLID STATE AND ROTATING DISK TYPES OF MEMORY Sep 26, 1991 Abandoned
Array ( [id] => 3058707 [patent_doc_number] => 05287480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Cache memory for independent parallel accessing by a plurality of processors' [patent_app_type] => 1 [patent_app_number] => 7/765818 [patent_app_country] => US [patent_app_date] => 1991-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2502 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287480.pdf [firstpage_image] =>[orig_patent_app_number] => 765818 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/765818
Cache memory for independent parallel accessing by a plurality of processors Sep 25, 1991 Issued
07/761538 METHOD AND APPARATUS FOR TRANSFERRING DATA WITHIN A COMPUTER USING A BURST SEQUENCE WHICH INCLUDES MODIFIED BYTES AND A MINIMUM NUMBER OF UNMODIFIED BYTES Sep 17, 1991 Abandoned
Array ( [id] => 3741690 [patent_doc_number] => 05671384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Work station with a DMA controller having extended addressing capability' [patent_app_type] => 1 [patent_app_number] => 7/752815 [patent_app_country] => US [patent_app_date] => 1991-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1902 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671384.pdf [firstpage_image] =>[orig_patent_app_number] => 752815 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/752815
Work station with a DMA controller having extended addressing capability Aug 29, 1991 Issued
Array ( [id] => 3660021 [patent_doc_number] => 05630098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks' [patent_app_type] => 1 [patent_app_number] => 7/752702 [patent_app_country] => US [patent_app_date] => 1991-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630098.pdf [firstpage_image] =>[orig_patent_app_number] => 752702 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/752702
System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks Aug 29, 1991 Issued
07/752006 IC MEMORY CARD HAVING MASKING FUNCTION FOR PREVENTING WRITING OF DATA INTO A FIXED MEMORY AREA Aug 28, 1991 Abandoned
Array ( [id] => 3058823 [patent_doc_number] => 05335334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Data processing apparatus having a real memory region with a corresponding fixed memory protection key value and method for allocating memories therefor' [patent_app_type] => 1 [patent_app_number] => 7/751778 [patent_app_country] => US [patent_app_date] => 1991-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/335/05335334.pdf [firstpage_image] =>[orig_patent_app_number] => 751778 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/751778
Data processing apparatus having a real memory region with a corresponding fixed memory protection key value and method for allocating memories therefor Aug 28, 1991 Issued
07/746318 BUFFER MEMORY MANAGEMENT TO PERMIT FRAGMENTATION Aug 15, 1991 Abandoned
Array ( [id] => 3102871 [patent_doc_number] => 05278969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Queue-length monitoring arrangement for detecting consistency between duplicate memories' [patent_app_type] => 1 [patent_app_number] => 7/739928 [patent_app_country] => US [patent_app_date] => 1991-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3296 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278969.pdf [firstpage_image] =>[orig_patent_app_number] => 739928 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/739928
Queue-length monitoring arrangement for detecting consistency between duplicate memories Aug 1, 1991 Issued
Array ( [id] => 3053374 [patent_doc_number] => 05377344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Selective memory transaction monitor system' [patent_app_type] => 1 [patent_app_number] => 7/739607 [patent_app_country] => US [patent_app_date] => 1991-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5188 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377344.pdf [firstpage_image] =>[orig_patent_app_number] => 739607 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/739607
Selective memory transaction monitor system Jul 30, 1991 Issued
07/734418 METHOD FOR PRIORITIZING MEMORY ACCESS REQUESTS USING A SELECTED PRIORITY CODE Jul 22, 1991 Abandoned
07/730147 MEMORY APPARATUS AND METHOD CAPABLE OF SETTING ATTRIBUTE OF INFORMATION TO BE CACHED Jul 14, 1991 Abandoned
07/726619 SYSTEM AND METHOD FOR REPLACING A DATA ENTRY IN A CACHE MEMORY. Jul 7, 1991 Abandoned
07/717133 TRANSLATION REQUEST BUFFER AND REQUESTOR TABLE FOR MINIMIZING THE NUMBER OF ACCESSES TO THE SAME ADDRESS Jun 17, 1991 Abandoned
07/716508 SEMICONDUCTOR MEMORY DEVICE Jun 16, 1991 Abandoned
07/716207 BY ENHANCED CACHE OPERATION WITH REMAPPING PAGES FOR ADDRESSES CAUSING CACHE MISSES Jun 16, 1991 Abandoned
Array ( [id] => 3744194 [patent_doc_number] => 05636363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Hardware control structure and method for off-chip monitoring entries of an on-chip cache' [patent_app_type] => 1 [patent_app_number] => 7/715525 [patent_app_country] => US [patent_app_date] => 1991-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4568 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636363.pdf [firstpage_image] =>[orig_patent_app_number] => 715525 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/715525
Hardware control structure and method for off-chip monitoring entries of an on-chip cache Jun 13, 1991 Issued
07/717776 STRUCTURE AND METHOD FOR A MULTIPLE LEVEL READ BUFFER SUPPORTING OPTIMAL THROTTLED READ OPERATIONS Jun 13, 1991 Abandoned
07/710490 MICROCOMPUTER WITH PROGRAMMABLE STATE MONITORING SYSTEM Jun 4, 1991 Abandoned
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