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Troy Chambers

Supervisory Patent Examiner (ID: 10357, Phone: (571)272-6874 , Office: P/3641 )

Most Active Art Unit
3641
Art Unit(s)
3658, 3641
Total Applications
1158
Issued Applications
719
Pending Applications
123
Abandoned Applications
316
Applications
StatisticsSubscription-Only

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3032683 [patent_doc_number] => 05303360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Programmable boundary between system board memory and slot bus memory' [patent_app_type] => 1 [patent_app_number] => 7/659588 [patent_app_country] => US [patent_app_date] => 1991-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1701 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303360.pdf [firstpage_image] =>[orig_patent_app_number] => 659588 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/659588 		Programmable boundary between system board memory and slot bus memory Feb 21, 1991 Issued
Array ( [id] => 3004236 [patent_doc_number] => 05347643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Bus system for coordinating internal and external direct memory access controllers' [patent_app_type] => 1 [patent_app_number] => 7/656676 [patent_app_country] => US [patent_app_date] => 1991-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5622 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347643.pdf [firstpage_image] =>[orig_patent_app_number] => 656676 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/656676 		Bus system for coordinating internal and external direct memory access controllers Feb 18, 1991 Issued
Array ( [id] => 3064768 [patent_doc_number] => 05307471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Memory controller for sub-memory unit such as disk drives' [patent_app_type] => 1 [patent_app_number] => 7/648168 [patent_app_country] => US [patent_app_date] => 1991-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3717 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307471.pdf [firstpage_image] =>[orig_patent_app_number] => 648168 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/648168 		Memory controller for sub-memory unit such as disk drives Jan 30, 1991 Issued
07/648998 READ/ WRITE CONTROL OF DATA STORAGE DISK UNITS Jan 30, 1991 Abandoned
07/641236 COMPUTER SYSTEM WITH MULTI-BUFFER DATA CACHE Jan 14, 1991 Abandoned
07/641217 DATA PROCESSOR WITH CACHE SYSTEM AND DATA ACCESS METHOD THEREFOR Jan 14, 1991 Abandoned
07/626078 AUTOMATIC OPTIMIZATION OF A COMPILED MEMORY STRUCTURE BASED ON USER SELECTED CRITERIA Dec 9, 1990 Abandoned
Array ( [id] => 3739261 [patent_doc_number] => 05652912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Versatile memory controller chip for concurrent input/output operations' [patent_app_type] => 1 [patent_app_number] => 7/618986 [patent_app_country] => US [patent_app_date] => 1990-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6234 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652912.pdf [firstpage_image] =>[orig_patent_app_number] => 618986 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/618986 		Versatile memory controller chip for concurrent input/output operations Nov 27, 1990 Issued
07/616653 MEMORY DEVICE HAVING ADDRESS TRANSLATER AND COMPARATOR FOR COMPARING MEMORY CELL ARRAY OUTPUTS Nov 20, 1990 Abandoned
Array ( [id] => 3701507 [patent_doc_number] => 05644786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method for scheduling the execution of disk I/O operations' [patent_app_type] => 1 [patent_app_number] => 7/610633 [patent_app_country] => US [patent_app_date] => 1990-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3451 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644786.pdf [firstpage_image] =>[orig_patent_app_number] => 610633 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/610633 		Method for scheduling the execution of disk I/O operations Nov 7, 1990 Issued
07/608146 MEMORY CONTROL UNIT Oct 31, 1990 Abandoned
Array ( [id] => 3105217 [patent_doc_number] => 05291442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Method and apparatus for dynamic cache line sectoring in multiprocessor systems' [patent_app_type] => 1 [patent_app_number] => 7/606242 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291442.pdf [firstpage_image] =>[orig_patent_app_number] => 606242 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/606242 		Method and apparatus for dynamic cache line sectoring in multiprocessor systems Oct 30, 1990 Issued
07/604023 CACHE MEMORY WITH N-WAY ASSOCIATION USING COMMON SENSE AMPLIFIERS Oct 24, 1990 Abandoned
Array ( [id] => 3502125 [patent_doc_number] => 05471639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Apparatus for arbitrating for a high speed direct memory access bus' [patent_app_type] => 1 [patent_app_number] => 7/602610 [patent_app_country] => US [patent_app_date] => 1990-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3674 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471639.pdf [firstpage_image] =>[orig_patent_app_number] => 602610 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/602610 		Apparatus for arbitrating for a high speed direct memory access bus Oct 23, 1990 Issued
07/605212 DATA CACHE PREFETCHING UNDER CONTROL OF INSTRUCTION CACHE Oct 23, 1990 Abandoned
07/601992 BUFFER MEMORY AND CONTROL CIRCUIT FOR IMPROVED DATA EXCHANGE Oct 22, 1990 Abandoned
07/599510 METHOD AND APPARATUS FOR A SINGLE INSRUCTION OPERATING MULTIPLE PROCESSORS ON A MEMORY CHIP Oct 17, 1990 Abandoned
07/593763 HIERARCHICAL INTEGRATED CIRCUIT CACHE MEMORY Oct 4, 1990 Abandoned
07/592162 DMA MULTIMODE TRANSFER CONTROL Oct 2, 1990 Abandoned
Array ( [id] => 3605982 [patent_doc_number] => 05522064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Data processing apparatus for dynamically setting timings in a dynamic memory system' [patent_app_type] => 1 [patent_app_number] => 7/590978 [patent_app_country] => US [patent_app_date] => 1990-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4648 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/522/05522064.pdf [firstpage_image] =>[orig_patent_app_number] => 590978 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/590978 		Data processing apparatus for dynamically setting timings in a dynamic memory system Sep 30, 1990 Issued
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