
Tse W. Chen
Supervisory Patent Examiner (ID: 2558, Phone: (571)272-3672 , Office: P/3777 )
| Most Active Art Unit | 2116 |
| Art Unit(s) | 3791, 2116, 3793, 3777 |
| Total Applications | 348 |
| Issued Applications | 185 |
| Pending Applications | 29 |
| Abandoned Applications | 135 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 731313
[patent_doc_number] => 07047402
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-16
[patent_title] => 'Process for booting and causing completion of synchronization based on multiple actuations of designated key when the system is off'
[patent_app_type] => utility
[patent_app_number] => 10/143744
[patent_app_country] => US
[patent_app_date] => 2002-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3175
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/047/07047402.pdf
[firstpage_image] =>[orig_patent_app_number] => 10143744
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/143744 | Process for booting and causing completion of synchronization based on multiple actuations of designated key when the system is off | May 9, 2002 | Issued |
Array
(
[id] => 619800
[patent_doc_number] => 07146518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Filter circuit with automatic adjustment of cutoff frequency via average signal values'
[patent_app_type] => utility
[patent_app_number] => 10/142311
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4789
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 327
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/146/07146518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10142311
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142311 | Filter circuit with automatic adjustment of cutoff frequency via average signal values | May 8, 2002 | Issued |
Array
(
[id] => 684828
[patent_doc_number] => 07085940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Floating point unit power reduction via inhibiting register file write during tight loop execution'
[patent_app_type] => utility
[patent_app_number] => 10/143365
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3196
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085940.pdf
[firstpage_image] =>[orig_patent_app_number] => 10143365
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/143365 | Floating point unit power reduction via inhibiting register file write during tight loop execution | May 8, 2002 | Issued |
Array
(
[id] => 947737
[patent_doc_number] => 06966006
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'Adaptive startup policy for accelerating multi-disk array spin-up'
[patent_app_type] => utility
[patent_app_number] => 10/142142
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 5841
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/966/06966006.pdf
[firstpage_image] =>[orig_patent_app_number] => 10142142
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142142 | Adaptive startup policy for accelerating multi-disk array spin-up | May 8, 2002 | Issued |
Array
(
[id] => 659386
[patent_doc_number] => 07111157
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-09-19
[patent_title] => 'Spurious input detection for firmware'
[patent_app_type] => utility
[patent_app_number] => 10/142402
[patent_app_country] => US
[patent_app_date] => 2002-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3155
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/111/07111157.pdf
[firstpage_image] =>[orig_patent_app_number] => 10142402
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142402 | Spurious input detection for firmware | May 7, 2002 | Issued |
Array
(
[id] => 619798
[patent_doc_number] => 07146517
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Clock pulse shaver with selective enable pulse width'
[patent_app_type] => utility
[patent_app_number] => 10/137060
[patent_app_country] => US
[patent_app_date] => 2002-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 16
[patent_no_of_words] => 2022
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/146/07146517.pdf
[firstpage_image] =>[orig_patent_app_number] => 10137060
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137060 | Clock pulse shaver with selective enable pulse width | May 1, 2002 | Issued |
Array
(
[id] => 490378
[patent_doc_number] => 07222245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-22
[patent_title] => 'Managing system power based on utilization statistics'
[patent_app_type] => utility
[patent_app_number] => 10/132931
[patent_app_country] => US
[patent_app_date] => 2002-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 9
[patent_no_of_words] => 7678
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/222/07222245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10132931
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/132931 | Managing system power based on utilization statistics | Apr 25, 2002 | Issued |
Array
(
[id] => 6265637
[patent_doc_number] => 20020188880
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-12
[patent_title] => 'System and method for reducing power consumption by a liquid crystal display'
[patent_app_type] => new
[patent_app_number] => 10/131959
[patent_app_country] => US
[patent_app_date] => 2002-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3204
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20020188880.pdf
[firstpage_image] =>[orig_patent_app_number] => 10131959
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/131959 | System and method for reducing power consumption by a liquid crystal display | Apr 24, 2002 | Abandoned |
Array
(
[id] => 6431470
[patent_doc_number] => 20020175839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Method and apparatus for a signal processing circuit'
[patent_app_type] => new
[patent_app_number] => 10/132674
[patent_app_country] => US
[patent_app_date] => 2002-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2936
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20020175839.pdf
[firstpage_image] =>[orig_patent_app_number] => 10132674
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/132674 | Method and apparatus for a signal processing circuit | Apr 24, 2002 | Abandoned |
Array
(
[id] => 629901
[patent_doc_number] => 07137017
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-14
[patent_title] => 'Method and apparatus for controlling processor operation speed'
[patent_app_type] => utility
[patent_app_number] => 10/472304
[patent_app_country] => US
[patent_app_date] => 2002-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 4569
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/137/07137017.pdf
[firstpage_image] =>[orig_patent_app_number] => 10472304
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/472304 | Method and apparatus for controlling processor operation speed | Apr 23, 2002 | Issued |
Array
(
[id] => 6784467
[patent_doc_number] => 20030065915
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'Method for initializing computer system'
[patent_app_type] => new
[patent_app_number] => 10/131625
[patent_app_country] => US
[patent_app_date] => 2002-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2460
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20030065915.pdf
[firstpage_image] =>[orig_patent_app_number] => 10131625
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/131625 | Method for initializing computer system | Apr 22, 2002 | Abandoned |
Array
(
[id] => 6830957
[patent_doc_number] => 20030182015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Polisher'
[patent_app_type] => new
[patent_app_number] => 10/101573
[patent_app_country] => US
[patent_app_date] => 2002-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3917
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20030182015.pdf
[firstpage_image] =>[orig_patent_app_number] => 10101573
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/101573 | Polisher | Mar 18, 2002 | Abandoned |
Array
(
[id] => 6836135
[patent_doc_number] => 20030163681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Processor with versatile external memory interface'
[patent_app_type] => new
[patent_app_number] => 10/083814
[patent_app_country] => US
[patent_app_date] => 2002-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3092
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20030163681.pdf
[firstpage_image] =>[orig_patent_app_number] => 10083814
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/083814 | Processor with versatile external memory interface | Feb 26, 2002 | Issued |
Array
(
[id] => 922578
[patent_doc_number] => 07321976
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-22
[patent_title] => 'Information processing apparatus, power supply control method for plural information processing apparatuses, and storage medium therefore'
[patent_app_type] => utility
[patent_app_number] => 10/082176
[patent_app_country] => US
[patent_app_date] => 2002-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 7708
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/321/07321976.pdf
[firstpage_image] =>[orig_patent_app_number] => 10082176
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/082176 | Information processing apparatus, power supply control method for plural information processing apparatuses, and storage medium therefore | Feb 25, 2002 | Issued |
Array
(
[id] => 6836204
[patent_doc_number] => 20030163750
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Clock grid skew reduction technique using biasable delay drivers'
[patent_app_type] => new
[patent_app_number] => 10/082892
[patent_app_country] => US
[patent_app_date] => 2002-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5204
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20030163750.pdf
[firstpage_image] =>[orig_patent_app_number] => 10082892
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/082892 | Clock grid skew reduction technique using biasable delay drivers | Feb 25, 2002 | Abandoned |
Array
(
[id] => 6707634
[patent_doc_number] => 20030154368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-14
[patent_title] => 'Method and system for linking firmware modules in a pre-memory execution environment'
[patent_app_type] => new
[patent_app_number] => 10/073495
[patent_app_country] => US
[patent_app_date] => 2002-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6620
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0154/20030154368.pdf
[firstpage_image] =>[orig_patent_app_number] => 10073495
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/073495 | Method and system for linking firmware modules in a pre-memory execution environment | Feb 10, 2002 | Issued |
Array
(
[id] => 6310077
[patent_doc_number] => 20020095437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-18
[patent_title] => 'Information processing apparatus, method for utilizing the same and program for information processing apparatus'
[patent_app_type] => new
[patent_app_number] => 10/043163
[patent_app_country] => US
[patent_app_date] => 2002-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2096
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20020095437.pdf
[firstpage_image] =>[orig_patent_app_number] => 10043163
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/043163 | Information processing apparatus, method for utilizing the same and program for information processing apparatus | Jan 13, 2002 | Abandoned |
Array
(
[id] => 6857774
[patent_doc_number] => 20030131275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'Microcontroller and system having a clock generator'
[patent_app_type] => new
[patent_app_number] => 10/040898
[patent_app_country] => US
[patent_app_date] => 2002-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1979
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20030131275.pdf
[firstpage_image] =>[orig_patent_app_number] => 10040898
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/040898 | Microcontroller and system having a clock generator | Jan 8, 2002 | Abandoned |
Array
(
[id] => 7174973
[patent_doc_number] => 20040078660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'System and method for minimizing upsets in digital microcircuits'
[patent_app_type] => new
[patent_app_number] => 10/043368
[patent_app_country] => US
[patent_app_date] => 2002-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3000
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20040078660.pdf
[firstpage_image] =>[orig_patent_app_number] => 10043368
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/043368 | System and method for minimizing upsets in digital microcircuits via ambient radiation monitoring | Jan 8, 2002 | Issued |
Array
(
[id] => 5791458
[patent_doc_number] => 20020161968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Memory system having stub bus configuration'
[patent_app_type] => new
[patent_app_number] => 10/043047
[patent_app_country] => US
[patent_app_date] => 2002-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6544
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20020161968.pdf
[firstpage_image] =>[orig_patent_app_number] => 10043047
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/043047 | Memory system having stub bus configuration | Jan 8, 2002 | Issued |