
Tu Ba Hoang
Examiner (ID: 6278)
| Most Active Art Unit | 3761 |
| Art Unit(s) | 3761, 2106, 3742, 2832 |
| Total Applications | 2049 |
| Issued Applications | 1536 |
| Pending Applications | 181 |
| Abandoned Applications | 331 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16355170
[patent_doc_number] => 10795680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-06
[patent_title] => Vector friendly instruction format and execution thereof
[patent_app_type] => utility
[patent_app_number] => 16/289506
[patent_app_country] => US
[patent_app_date] => 2019-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 78
[patent_no_of_words] => 31638
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289506
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/289506 | Vector friendly instruction format and execution thereof | Feb 27, 2019 | Issued |
Array
(
[id] => 16431422
[patent_doc_number] => 10831504
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Processor with hybrid pipeline capable of operating in out-of-order and in-order modes
[patent_app_type] => utility
[patent_app_number] => 16/150051
[patent_app_country] => US
[patent_app_date] => 2018-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13620
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150051
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/150051 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Oct 1, 2018 | Issued |
Array
(
[id] => 14009333
[patent_doc_number] => 10223125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-05
[patent_title] => Linkable issue queue parallel execution slice processing method
[patent_app_type] => utility
[patent_app_number] => 16/048946
[patent_app_country] => US
[patent_app_date] => 2018-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7168
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 299
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048946
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/048946 | Linkable issue queue parallel execution slice processing method | Jul 29, 2018 | Issued |
Array
(
[id] => 14457529
[patent_doc_number] => 10324725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-18
[patent_title] => Fault detection in instruction translations
[patent_app_type] => utility
[patent_app_number] => 15/915975
[patent_app_country] => US
[patent_app_date] => 2018-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 6534
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915975
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/915975 | Fault detection in instruction translations | Mar 7, 2018 | Issued |
Array
(
[id] => 14379141
[patent_doc_number] => 20190163483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => SCALABLE DEPENDENCY MATRIX WITH WAKE-UP COLUMNS FOR LONG LATENCY INSTRUCTIONS IN AN OUT-OF-ORDER PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/826742
[patent_app_country] => US
[patent_app_date] => 2017-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10256
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826742
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/826742 | Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor | Nov 29, 2017 | Issued |
Array
(
[id] => 12241963
[patent_doc_number] => 20180074825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-15
[patent_title] => 'APPARATUS AND METHOD OF IMPROVED INSERT INSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 15/809721
[patent_app_country] => US
[patent_app_date] => 2017-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 23160
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809721
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/809721 | Apparatus and method of improved insert instructions | Nov 9, 2017 | Issued |
Array
(
[id] => 16185984
[patent_doc_number] => 10719316
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Apparatus and method of improved packed integer permute instruction
[patent_app_type] => utility
[patent_app_number] => 15/808800
[patent_app_country] => US
[patent_app_date] => 2017-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 43
[patent_no_of_words] => 21974
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808800
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/808800 | Apparatus and method of improved packed integer permute instruction | Nov 8, 2017 | Issued |
Array
(
[id] => 12234977
[patent_doc_number] => 20180067840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-08
[patent_title] => 'INSTRUCTION GENERATION'
[patent_app_type] => utility
[patent_app_number] => 15/807921
[patent_app_country] => US
[patent_app_date] => 2017-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4879
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807921
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/807921 | Instruction generation based on selection or non-selection of a special command | Nov 8, 2017 | Issued |
Array
(
[id] => 12241958
[patent_doc_number] => 20180074822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-15
[patent_title] => 'APPARATUS AND METHOD OF IMPROVED PERMUTE INSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 15/808788
[patent_app_country] => US
[patent_app_date] => 2017-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 23194
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808788
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/808788 | Apparatus and method of improved permute instructions | Nov 8, 2017 | Issued |
Array
(
[id] => 12331638
[patent_doc_number] => 09946540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-17
[patent_title] => Apparatus and method of improved permute instructions with multiple granularities
[patent_app_type] => utility
[patent_app_number] => 15/601960
[patent_app_country] => US
[patent_app_date] => 2017-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 43
[patent_no_of_words] => 21951
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601960
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/601960 | Apparatus and method of improved permute instructions with multiple granularities | May 21, 2017 | Issued |
Array
(
[id] => 16408743
[patent_doc_number] => 10817295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-27
[patent_title] => Thread-level sleep in a multithreaded architecture
[patent_app_type] => utility
[patent_app_number] => 15/582549
[patent_app_country] => US
[patent_app_date] => 2017-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7960
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582549
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/582549 | Thread-level sleep in a multithreaded architecture | Apr 27, 2017 | Issued |
Array
(
[id] => 11759220
[patent_doc_number] => 20170206089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-20
[patent_title] => 'INFORMATION PROCESSING APPARATUS AND COMPUTATIONAL METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/373147
[patent_app_country] => US
[patent_app_date] => 2016-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 11188
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15373147
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/373147 | INFORMATION PROCESSING APPARATUS AND COMPUTATIONAL METHOD | Dec 7, 2016 | Abandoned |
Array
(
[id] => 15886883
[patent_doc_number] => 10649786
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Reduced stack usage in a multithreaded processor
[patent_app_type] => utility
[patent_app_number] => 15/367008
[patent_app_country] => US
[patent_app_date] => 2016-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 6
[patent_no_of_words] => 8928
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367008
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/367008 | Reduced stack usage in a multithreaded processor | Nov 30, 2016 | Issued |
Array
(
[id] => 12796969
[patent_doc_number] => 20180157492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => MEMORY ACCESS CONTROL FOR PARALLELIZED PROCESSING
[patent_app_type] => utility
[patent_app_number] => 15/366009
[patent_app_country] => US
[patent_app_date] => 2016-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12418
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366009
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/366009 | MEMORY ACCESS CONTROL FOR PARALLELIZED PROCESSING | Nov 30, 2016 | Abandoned |
Array
(
[id] => 14123133
[patent_doc_number] => 10248425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Processor with slave free list that handles overflow of recycled physical registers and method of recycling physical registers in a processor using a slave free list
[patent_app_type] => utility
[patent_app_number] => 15/235662
[patent_app_country] => US
[patent_app_date] => 2016-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8105
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235662
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/235662 | Processor with slave free list that handles overflow of recycled physical registers and method of recycling physical registers in a processor using a slave free list | Aug 11, 2016 | Issued |
Array
(
[id] => 12454056
[patent_doc_number] => 09983883
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-29
[patent_title] => Transaction abort instruction specifying a reason for abort
[patent_app_type] => utility
[patent_app_number] => 15/232299
[patent_app_country] => US
[patent_app_date] => 2016-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 26419
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232299
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/232299 | Transaction abort instruction specifying a reason for abort | Aug 8, 2016 | Issued |
Array
(
[id] => 12495225
[patent_doc_number] => 09996360
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-12
[patent_title] => Transaction abort instruction specifying a reason for abort
[patent_app_type] => utility
[patent_app_number] => 15/232271
[patent_app_country] => US
[patent_app_date] => 2016-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 26443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232271
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/232271 | Transaction abort instruction specifying a reason for abort | Aug 8, 2016 | Issued |
Array
(
[id] => 11494356
[patent_doc_number] => 20170068542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'PROCESSOR AND STORE INSTRUCTION CONVERSION METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/230930
[patent_app_country] => US
[patent_app_date] => 2016-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7856
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230930
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/230930 | PROCESSOR AND STORE INSTRUCTION CONVERSION METHOD | Aug 7, 2016 | Abandoned |
Array
(
[id] => 12094429
[patent_doc_number] => 20170351522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-07
[patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING LOAD-HIT-STORE HANDLING'
[patent_app_type] => utility
[patent_app_number] => 15/170208
[patent_app_country] => US
[patent_app_date] => 2016-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9791
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170208
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/170208 | Operation of a multi-slice processor implementing load-hit-store handling | May 31, 2016 | Issued |
Array
(
[id] => 12986023
[patent_doc_number] => 20170344368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-30
[patent_title] => IDENTIFYING AN EFFECTIVE ADDRESS (EA) USING AN INTERRUPT INSTRUCTION TAG (ITAG) IN A MULTI-SLICE PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/168560
[patent_app_country] => US
[patent_app_date] => 2016-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8449
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15168560
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/168560 | Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor | May 30, 2016 | Issued |