Tu Tu V. Ho

Array ( [id] => 616381 [patent_doc_number] => 07144792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Method and apparatus for fabricating and connecting a semiconductor power switching device' [patent_app_type] => utility [patent_app_number] => 10/975830 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3392 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/144/07144792.pdf [firstpage_image] =>[orig_patent_app_number] => 10975830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 278298 [patent_doc_number] => 07557375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Method for fabricating crystalline silicon' [patent_app_type] => utility [patent_app_number] => 10/974390 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4255 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557375.pdf [firstpage_image] =>[orig_patent_app_number] => 10974390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7225842 [patent_doc_number] => 20050078534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Trench buried bit line memory devices and methods thereof' [patent_app_type] => utility [patent_app_number] => 10/968429 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7526 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20050078534.pdf [firstpage_image] =>[orig_patent_app_number] => 10968429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 502993 [patent_doc_number] => 07205606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'DRAM access transistor' [patent_app_type] => utility [patent_app_number] => 10/962665 [patent_app_country] => US [patent_app_date] => 2004-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5232 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205606.pdf [firstpage_image] =>[orig_patent_app_number] => 10962665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1018665 [patent_doc_number] => 06891241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Single transistor type magnetic random access memory device and method of operating and manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/950582 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3371 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891241.pdf [firstpage_image] =>[orig_patent_app_number] => 10950582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547106 [patent_doc_number] => 07166863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Semiconductor element, semiconductor device, electronic device, TV set and digital camera' [patent_app_type] => utility [patent_app_number] => 10/941823 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 129 [patent_no_of_words] => 23513 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166863.pdf [firstpage_image] =>[orig_patent_app_number] => 10941823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 659686 [patent_doc_number] => 07105912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Resistor structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/711390 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2208 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105912.pdf [firstpage_image] =>[orig_patent_app_number] => 10711390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 609929 [patent_doc_number] => 07151313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => 'Method of forming wirings for tile-shaped elements, structures of wirings for tile-shaped elements, and electronic equipment' [patent_app_type] => utility [patent_app_number] => 10/934600 [patent_app_country] => US [patent_app_date] => 2004-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 12455 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151313.pdf [firstpage_image] =>[orig_patent_app_number] => 10934600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7198047 [patent_doc_number] => 20050051763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Nanophase multilayer barrier and process' [patent_app_type] => utility [patent_app_number] => 10/934530 [patent_app_country] => US [patent_app_date] => 2004-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8483 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051763.pdf [firstpage_image] =>[orig_patent_app_number] => 10934530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7126248 [patent_doc_number] => 20050057992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Magnetoresistance effect element, method of manufacture thereof, magnetic storage and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 10/933418 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6855 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057992.pdf [firstpage_image] =>[orig_patent_app_number] => 10933418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6916900 [patent_doc_number] => 20050094461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Integrated semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/932888 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094461.pdf [firstpage_image] =>[orig_patent_app_number] => 10932888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 668923 [patent_doc_number] => 07095122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same' [patent_app_type] => utility [patent_app_number] => 10/932840 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4912 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095122.pdf [firstpage_image] =>[orig_patent_app_number] => 10932840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5898216 [patent_doc_number] => 20060043449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors' [patent_app_type] => utility [patent_app_number] => 10/932150 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6331 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043449.pdf [firstpage_image] =>[orig_patent_app_number] => 10932150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 664110 [patent_doc_number] => 07102205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Bipolar transistor with extrinsic stress layer' [patent_app_type] => utility [patent_app_number] => 10/931660 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5373 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102205.pdf [firstpage_image] =>[orig_patent_app_number] => 10931660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5898377 [patent_doc_number] => 20060043610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Power controller with bond wire fuse' [patent_app_type] => utility [patent_app_number] => 10/931950 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1744 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043610.pdf [firstpage_image] =>[orig_patent_app_number] => 10931950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 961319 [patent_doc_number] => 06952032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Programmable array logic or memory devices with asymmetrical tunnel barriers' [patent_app_type] => utility [patent_app_number] => 10/931540 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 14355 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952032.pdf [firstpage_image] =>[orig_patent_app_number] => 10931540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 503234 [patent_doc_number] => 07205638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Silicon building blocks in integrated circuit packaging' [patent_app_type] => utility [patent_app_number] => 10/931497 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205638.pdf [firstpage_image] =>[orig_patent_app_number] => 10931497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 703163 [patent_doc_number] => 07064430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Stacked die packaging and fabrication method' [patent_app_type] => utility [patent_app_number] => 10/931919 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5266 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064430.pdf [firstpage_image] =>[orig_patent_app_number] => 10931919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 634564 [patent_doc_number] => 07129567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements' [patent_app_type] => utility [patent_app_number] => 10/931959 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 48 [patent_no_of_words] => 15568 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129567.pdf [firstpage_image] =>[orig_patent_app_number] => 10931959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 738904 [patent_doc_number] => 07034372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'HGA dynamics testing with shear mode piezo transducers' [patent_app_type] => utility [patent_app_number] => 10/930918 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2766 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034372.pdf [firstpage_image] =>[orig_patent_app_number] => 10930918 [rel_patent_id] =>[rel_patent_doc_number] =>)