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Tu Tu V. Ho

Examiner (ID: 15910)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2804
Issued Applications
2592
Pending Applications
124
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7314239 [patent_doc_number] => 20040222439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Optical power monitoring for a semiconductor laser device' [patent_app_type] => new [patent_app_number] => 10/775910 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1730 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222439.pdf [firstpage_image] =>[orig_patent_app_number] => 10775910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/775910
Optical power monitoring for a semiconductor laser device Feb 9, 2004 Issued
Array ( [id] => 717129 [patent_doc_number] => 07053455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/772280 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5636 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/053/07053455.pdf [firstpage_image] =>[orig_patent_app_number] => 10772280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/772280
Semiconductor device and method of manufacturing semiconductor device Feb 5, 2004 Issued
Array ( [id] => 1025493 [patent_doc_number] => 06885054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same' [patent_app_type] => utility [patent_app_number] => 10/772210 [patent_app_country] => US [patent_app_date] => 2004-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4128 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/885/06885054.pdf [firstpage_image] =>[orig_patent_app_number] => 10772210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/772210
Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same Feb 3, 2004 Issued
Array ( [id] => 954097 [patent_doc_number] => 06958512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-25 [patent_title] => 'Non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 10/770010 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4284 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958512.pdf [firstpage_image] =>[orig_patent_app_number] => 10770010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770010
Non-volatile memory device Feb 2, 2004 Issued
Array ( [id] => 979320 [patent_doc_number] => 06930325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Test structure for improved vertical memory arrays' [patent_app_type] => utility [patent_app_number] => 10/766902 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930325.pdf [firstpage_image] =>[orig_patent_app_number] => 10766902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766902
Test structure for improved vertical memory arrays Jan 29, 2004 Issued
Array ( [id] => 1031437 [patent_doc_number] => 06878991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Vertical device 4F2 EEPROM memory' [patent_app_type] => utility [patent_app_number] => 10/769116 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 9746 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878991.pdf [firstpage_image] =>[orig_patent_app_number] => 10769116 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769116
Vertical device 4F2 EEPROM memory Jan 29, 2004 Issued
Array ( [id] => 7338714 [patent_doc_number] => 20040245653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Flip chip package having protective cap and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/766210 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3622 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20040245653.pdf [firstpage_image] =>[orig_patent_app_number] => 10766210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766210
Flip chip package having protective cap and method of fabricating the same Jan 28, 2004 Abandoned
Array ( [id] => 539924 [patent_doc_number] => 07176545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Apparatus and methods for maskless pattern generation' [patent_app_type] => utility [patent_app_number] => 10/766629 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 106 [patent_no_of_words] => 27007 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176545.pdf [firstpage_image] =>[orig_patent_app_number] => 10766629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766629
Apparatus and methods for maskless pattern generation Jan 26, 2004 Issued
Array ( [id] => 7183515 [patent_doc_number] => 20050161820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Integrated circuit with conductive grid for power distribution' [patent_app_type] => utility [patent_app_number] => 10/765810 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2912 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161820.pdf [firstpage_image] =>[orig_patent_app_number] => 10765810 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765810
Integrated circuit with conductive grid for power distribution Jan 26, 2004 Abandoned
Array ( [id] => 7414704 [patent_doc_number] => 20040159869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Memory array with high temperature wiring' [patent_app_type] => new [patent_app_number] => 10/765406 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5040 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159869.pdf [firstpage_image] =>[orig_patent_app_number] => 10765406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765406
Memory array with high temperature wiring Jan 25, 2004 Issued
Array ( [id] => 7677547 [patent_doc_number] => 20040152279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Semiconductor latches and SRAM devices' [patent_app_type] => new [patent_app_number] => 10/764048 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152279.pdf [firstpage_image] =>[orig_patent_app_number] => 10764048 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764048
Semiconductor latches and SRAM devices Jan 25, 2004 Issued
Array ( [id] => 7415243 [patent_doc_number] => 20040159943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Semiconductor device and method for designing the same' [patent_app_type] => new [patent_app_number] => 10/761310 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3335 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159943.pdf [firstpage_image] =>[orig_patent_app_number] => 10761310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761310
Semiconductor device and method for designing the same Jan 21, 2004 Issued
Array ( [id] => 7407066 [patent_doc_number] => 20040227173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Semiconductor devices with scalable two transistor memory cells and methods of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/763016 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6087 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227173.pdf [firstpage_image] =>[orig_patent_app_number] => 10763016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/763016
Semiconductor devices with scalable two transistor memory cells Jan 21, 2004 Issued
Array ( [id] => 7273002 [patent_doc_number] => 20040232453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/759609 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7877 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232453.pdf [firstpage_image] =>[orig_patent_app_number] => 10759609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759609
Method for manufacturing a semiconductor device Jan 15, 2004 Issued
Array ( [id] => 1093911 [patent_doc_number] => 06825526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Structure for increasing drive current in a memory array and related method' [patent_app_type] => B1 [patent_app_number] => 10/759809 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825526.pdf [firstpage_image] =>[orig_patent_app_number] => 10759809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759809
Structure for increasing drive current in a memory array and related method Jan 15, 2004 Issued
Array ( [id] => 6981173 [patent_doc_number] => 20050151241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'MULTILAYER CERAMIC SUBSTRATE WITH SINGLE VIA ANCHORED PAD AND METHOD OF FORMING' [patent_app_type] => utility [patent_app_number] => 10/707810 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2702 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151241.pdf [firstpage_image] =>[orig_patent_app_number] => 10707810 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707810
Multilayer ceramic substrate with single via anchored pad and method of forming Jan 13, 2004 Issued
Array ( [id] => 7420773 [patent_doc_number] => 20040183110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'MAGNETIC MEMORY UNIT AND MAGNETIC MEMORY ARRAY' [patent_app_type] => new [patent_app_number] => 10/754910 [patent_app_country] => US [patent_app_date] => 2004-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183110.pdf [firstpage_image] =>[orig_patent_app_number] => 10754910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/754910
Magnetic memory unit and magnetic memory array Jan 8, 2004 Issued
Array ( [id] => 1005902 [patent_doc_number] => 06906349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Polysilicon thin film transistor array panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/752510 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5557 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906349.pdf [firstpage_image] =>[orig_patent_app_number] => 10752510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752510
Polysilicon thin film transistor array panel and manufacturing method thereof Jan 7, 2004 Issued
Array ( [id] => 7612400 [patent_doc_number] => 06903437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods' [patent_app_type] => utility [patent_app_number] => 10/753914 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4517 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903437.pdf [firstpage_image] =>[orig_patent_app_number] => 10753914 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753914
Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods Jan 6, 2004 Issued
Array ( [id] => 7309228 [patent_doc_number] => 20040142526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Fuse boxes with guard rings for integrated circuits and integrated circuits including the same' [patent_app_type] => new [patent_app_number] => 10/752210 [patent_app_country] => US [patent_app_date] => 2004-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8954 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142526.pdf [firstpage_image] =>[orig_patent_app_number] => 10752210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752210
Fuse boxes with guard rings for integrated circuits and integrated circuits including the same Jan 5, 2004 Issued
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