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Tu Tu V. Ho

Examiner (ID: 11657, Phone: (571)272-1778 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2822
Issued Applications
2615
Pending Applications
114
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17738008 [patent_doc_number] => 20220223470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING COMPOSITE HARD MASKS FOR FORMATION OF DEEP VIA OPENINGS [patent_app_type] => utility [patent_app_number] => 17/657521 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 56968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657521
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings Mar 30, 2022 Issued
Array ( [id] => 18782287 [patent_doc_number] => 11824054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Package structure [patent_app_type] => utility [patent_app_number] => 17/705418 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 11603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705418 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705418
Package structure Mar 27, 2022 Issued
Array ( [id] => 17723547 [patent_doc_number] => 20220216269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => MEMORY DEVICE AND SEMICONDUCTOR DIE, AND METHOD OF FABRICATING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/703923 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703923
Memory device and semiconductor die, and method of fabricating memory device Mar 23, 2022 Issued
Array ( [id] => 18985409 [patent_doc_number] => 11910619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Method for MRAM top electrode connection [patent_app_type] => utility [patent_app_number] => 17/703065 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 9590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703065
Method for MRAM top electrode connection Mar 23, 2022 Issued
Array ( [id] => 18653284 [patent_doc_number] => 20230299124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => HIGH DENSITY CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/700380 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700380
High density capacitor Mar 20, 2022 Issued
Array ( [id] => 18768540 [patent_doc_number] => 11818964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Spacer scheme and method for MRAM [patent_app_type] => utility [patent_app_number] => 17/696333 [patent_app_country] => US [patent_app_date] => 2022-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 8122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/696333
Spacer scheme and method for MRAM Mar 15, 2022 Issued
Array ( [id] => 19132895 [patent_doc_number] => 20240138248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => A PROCESS OF FORMING AN ELECTRODE INTERCONNECTION IN AN INTEGRATED MULTILAYER THIN-FILM ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/548047 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/548047
A PROCESS OF FORMING AN ELECTRODE INTERCONNECTION IN AN INTEGRATED MULTILAYER THIN-FILM ELECTRONIC DEVICE Feb 28, 2022 Pending
Array ( [id] => 19132895 [patent_doc_number] => 20240138248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => A PROCESS OF FORMING AN ELECTRODE INTERCONNECTION IN AN INTEGRATED MULTILAYER THIN-FILM ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/548047 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/548047
A PROCESS OF FORMING AN ELECTRODE INTERCONNECTION IN AN INTEGRATED MULTILAYER THIN-FILM ELECTRONIC DEVICE Feb 28, 2022 Pending
Array ( [id] => 17780198 [patent_doc_number] => 20220246548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => Integrated Circuit Layout, Integrated Circuit, and Method for Fabricating the Same [patent_app_type] => utility [patent_app_number] => 17/676694 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676694
Integrated circuit layout, integrated circuit, and method for fabricating the same Feb 20, 2022 Issued
Array ( [id] => 19945360 [patent_doc_number] => 12317510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory array [patent_app_type] => utility [patent_app_number] => 17/673760 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2280 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673760
Memory array Feb 15, 2022 Issued
Array ( [id] => 18416035 [patent_doc_number] => 11670582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Package structure and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/671524 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671524
Package structure and method of fabricating the same Feb 13, 2022 Issued
Array ( [id] => 20229303 [patent_doc_number] => 12417959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Integrated circuit device cooling using thermoresponsive materials [patent_app_type] => utility [patent_app_number] => 17/668241 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6776 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668241
Integrated circuit device cooling using thermoresponsive materials Feb 8, 2022 Issued
Array ( [id] => 19741338 [patent_doc_number] => 12218186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Back-end-of-line passive device structure having common connection to ground [patent_app_type] => utility [patent_app_number] => 17/666285 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666285
Back-end-of-line passive device structure having common connection to ground Feb 6, 2022 Issued
Array ( [id] => 19814004 [patent_doc_number] => 12245434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings [patent_app_type] => utility [patent_app_number] => 17/590278 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 120 [patent_figures_cnt] => 187 [patent_no_of_words] => 51867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590278
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings Jan 31, 2022 Issued
Array ( [id] => 18533161 [patent_doc_number] => 20230238236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SELECTIVE DEPOSITION AND CROSS-LINKING OF POLYMERIC DIELECTRIC MATERIAL [patent_app_type] => utility [patent_app_number] => 17/586757 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586757
Selective deposition and cross-linking of polymeric dielectric material Jan 26, 2022 Issued
Array ( [id] => 18639530 [patent_doc_number] => 11764151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Connection of several circuits of an electronic chip [patent_app_type] => utility [patent_app_number] => 17/580055 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4939 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580055
Connection of several circuits of an electronic chip Jan 19, 2022 Issued
Array ( [id] => 17583375 [patent_doc_number] => 20220140230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => NANO-ROD SPIN ORBIT COUPLING BASED MAGNETIC RANDOM ACCESS MEMORY WITH SHAPE INDUCED PERPENDICULAR MAGNETIC ANISOTROPY [patent_app_type] => utility [patent_app_number] => 17/578093 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578093
Nano-rod spin orbit coupling based magnetic random access memory with shape induced perpendicular magnetic anisotropy Jan 17, 2022 Issued
Array ( [id] => 17583042 [patent_doc_number] => 20220139897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/577647 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577647
Three-dimensional semiconductor memory device Jan 17, 2022 Issued
Array ( [id] => 17582970 [patent_doc_number] => 20220139825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/573609 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573609 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573609
Semiconductor structure and manufacturing method thereof Jan 10, 2022 Issued
Array ( [id] => 20471017 [patent_doc_number] => 12527063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Nitride-based semiconductor circuit and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/637461 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 12285 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17637461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/637461
Nitride-based semiconductor circuit and method for manufacturing the same Jan 6, 2022 Issued
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