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Tu Tu V. Ho

Examiner (ID: 5391, Phone: (571)272-1778 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2862
Issued Applications
2634
Pending Applications
132
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20435065 [patent_doc_number] => 12506128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Package architecture of scalable compute wall having compute bricks with vertically stacked dies [patent_app_type] => utility [patent_app_number] => 17/853778 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 20855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853778
Package architecture of scalable compute wall having compute bricks with vertically stacked dies Jun 28, 2022 Issued
Array ( [id] => 18345362 [patent_doc_number] => 20230133472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SILICON WAFER AND EPITAXIAL SILICON WAFER [patent_app_type] => utility [patent_app_number] => 17/853469 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853469
Silicon wafer and epitaxial silicon wafer Jun 28, 2022 Issued
Array ( [id] => 19720355 [patent_doc_number] => 12205898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Metal-oxide-metal cell semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/853485 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853485
Metal-oxide-metal cell semiconductor device and method Jun 28, 2022 Issued
Array ( [id] => 18882978 [patent_doc_number] => 20240006347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => PASSIVE CIRCUIT ON A BACK-END-OF-LINE OF A PACKAGE [patent_app_type] => utility [patent_app_number] => 17/853572 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853572
Passive circuit on a back-end-of-line of a package Jun 28, 2022 Issued
Array ( [id] => 19935100 [patent_doc_number] => 12308308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Electronic package [patent_app_type] => utility [patent_app_number] => 17/853097 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853097
Electronic package Jun 28, 2022 Issued
Array ( [id] => 17949420 [patent_doc_number] => 20220336439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Integrated Standard Cell Structure [patent_app_type] => utility [patent_app_number] => 17/850067 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850067
Integrated standard cell structure Jun 26, 2022 Issued
Array ( [id] => 18865923 [patent_doc_number] => 20230420360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => INTEGRATED CIRCUIT STRUCTURE WITH RECESSED SELF-ALIGNED DEEP BOUNDARY VIA [patent_app_type] => utility [patent_app_number] => 17/850779 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850779
Integrated circuit structure with recessed self-aligned deep boundary via Jun 26, 2022 Issued
Array ( [id] => 17933244 [patent_doc_number] => 20220328370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MANUFACTURING METHOD OF CIRCUIT CARRIER WITH CHIP MOUNTED THEREON [patent_app_type] => utility [patent_app_number] => 17/849713 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849713
Manufacturing method of circuit carrier with chip mounted thereon Jun 26, 2022 Issued
Array ( [id] => 17949649 [patent_doc_number] => 20220336668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/850799 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850799
Dielectric isolation layer between a nanowire transistor and a substrate Jun 26, 2022 Issued
Array ( [id] => 18866056 [patent_doc_number] => 20230420493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MIM CAPACITOR AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/849930 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849930
MIM capacitor and method of forming the same Jun 26, 2022 Issued
Array ( [id] => 18865859 [patent_doc_number] => 20230420296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => INTERCONNECT WITH TWO-DIMENSIONAL FREE ZERO LINE END ENCLOSURE [patent_app_type] => utility [patent_app_number] => 17/808316 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808316
Interconnect with two-dimensional free zero line end enclosure Jun 22, 2022 Issued
Array ( [id] => 19919876 [patent_doc_number] => 12295272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Phase change memory [patent_app_type] => utility [patent_app_number] => 17/847016 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847016
Phase change memory Jun 21, 2022 Issued
Array ( [id] => 19277325 [patent_doc_number] => 12027457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure [patent_app_type] => utility [patent_app_number] => 17/836934 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 7811 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836934
Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure Jun 8, 2022 Issued
Array ( [id] => 18969516 [patent_doc_number] => 11903329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Reducing junction resistance variation in two-step deposition processes [patent_app_type] => utility [patent_app_number] => 17/836893 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13974 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836893
Reducing junction resistance variation in two-step deposition processes Jun 8, 2022 Issued
Array ( [id] => 18394816 [patent_doc_number] => 20230163037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/836155 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836155
Semiconductor device and method of manufacturing the same Jun 8, 2022 Issued
Array ( [id] => 18983663 [patent_doc_number] => 11908852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Layout designs of integrated circuits having backside routing tracks [patent_app_type] => utility [patent_app_number] => 17/833531 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 54 [patent_no_of_words] => 17048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833531
Layout designs of integrated circuits having backside routing tracks Jun 5, 2022 Issued
Array ( [id] => 20276494 [patent_doc_number] => 12446283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/831087 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 6303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831087
Semiconductor device and method for forming the same Jun 1, 2022 Issued
Array ( [id] => 18037504 [patent_doc_number] => 20220381720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => REFERENCE ELECTRODE, SYSTEM AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/827594 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827594
Reference electrode, system and method of manufacture May 26, 2022 Issued
Array ( [id] => 19965192 [patent_doc_number] => 12334714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Visible light-emitting device and laser with improved tolerance to crystalline defects and damage [patent_app_type] => utility [patent_app_number] => 17/751335 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 6893 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751335
Visible light-emitting device and laser with improved tolerance to crystalline defects and damage May 22, 2022 Issued
Array ( [id] => 17855327 [patent_doc_number] => 20220285370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => LAYOUT OF STATIC RANDOM ACCESS MEMORY PERIPHERY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/751426 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751426 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751426
Layout of static random access memory periphery circuit May 22, 2022 Issued
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