Tu Tu V. Ho

Array ( [id] => 1502385 [patent_doc_number] => 06486549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor module with encapsulant base' [patent_app_type] => B1 [patent_app_number] => 10/052810 [patent_app_country] => US [patent_app_date] => 2001-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 79 [patent_no_of_words] => 13915 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486549.pdf [firstpage_image] =>[orig_patent_app_number] => 10052810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6790074 [patent_doc_number] => 20030085418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'ON-DIE SWITCHING POWER CONVERTER WITH STEPPED SWITCH DRIVERS AND METHOD' [patent_app_type] => new [patent_app_number] => 10/010705 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4594 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20030085418.pdf [firstpage_image] =>[orig_patent_app_number] => 10010705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7615038 [patent_doc_number] => 06897488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Radiation-emitting chip' [patent_app_type] => utility [patent_app_number] => 10/415810 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897488.pdf [firstpage_image] =>[orig_patent_app_number] => 10415810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1518826 [patent_doc_number] => 06501117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Static self-refreshing DRAM structure and operating mode' [patent_app_type] => B1 [patent_app_number] => 10/007846 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 7567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501117.pdf [firstpage_image] =>[orig_patent_app_number] => 10007846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6867660 [patent_doc_number] => 20030080349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'POWER AMPLIFIER WITH BASE AND COLLECTOR STRAPS' [patent_app_type] => new [patent_app_number] => 10/004309 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5320 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20030080349.pdf [firstpage_image] =>[orig_patent_app_number] => 10004309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6635105 [patent_doc_number] => 20030006420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'METHOD OF FABRICATING ORGANIC LIGHT EMITTING DIODE' [patent_app_type] => new [patent_app_number] => 10/020810 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1778 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006420.pdf [firstpage_image] =>[orig_patent_app_number] => 10020810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5872763 [patent_doc_number] => 20020048202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method of managing a defect in a flash memory' [patent_app_type] => new [patent_app_number] => 09/978014 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4857 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048202.pdf [firstpage_image] =>[orig_patent_app_number] => 09978014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1341755 [patent_doc_number] => 06586347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method and structure to improve the reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal layers in semiconductor integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/978229 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2094 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586347.pdf [firstpage_image] =>[orig_patent_app_number] => 09978229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6812640 [patent_doc_number] => 20030072190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING DISTURB TEST CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/976116 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6194 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20030072190.pdf [firstpage_image] =>[orig_patent_app_number] => 09976116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6520089 [patent_doc_number] => 20020136067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE ARCHITECTURE' [patent_app_type] => new [patent_app_number] => 09/913010 [patent_app_country] => US [patent_app_date] => 2001-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9441 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136067.pdf [firstpage_image] =>[orig_patent_app_number] => 09913010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1504286 [patent_doc_number] => 06487101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Use of search lines as global bitlines in a cam design' [patent_app_type] => B1 [patent_app_number] => 09/968814 [patent_app_country] => US [patent_app_date] => 2001-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2853 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487101.pdf [firstpage_image] =>[orig_patent_app_number] => 09968814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1422193 [patent_doc_number] => 06518613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Memory cell configuration with capacitor on opposite surface of substrate and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 09/968304 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3802 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518613.pdf [firstpage_image] =>[orig_patent_app_number] => 09968304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6584503 [patent_doc_number] => 20020041513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Variable capacitor and memory device employing the same' [patent_app_type] => new [patent_app_number] => 09/964510 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4028 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041513.pdf [firstpage_image] =>[orig_patent_app_number] => 09964510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1411661 [patent_doc_number] => 06532176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Non-volatile memory array with equalized bit line potentials' [patent_app_type] => B1 [patent_app_number] => 09/963912 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4223 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532176.pdf [firstpage_image] =>[orig_patent_app_number] => 09963912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6673122 [patent_doc_number] => 20030058725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'ANTIFUSE PROGRAMMING CURRENT LIMITER' [patent_app_type] => new [patent_app_number] => 09/964110 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3882 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058725.pdf [firstpage_image] =>[orig_patent_app_number] => 09964110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1572663 [patent_doc_number] => 06498748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Nonvolatile memory with illegitimate read preventing capability' [patent_app_type] => B2 [patent_app_number] => 09/960509 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5090 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498748.pdf [firstpage_image] =>[orig_patent_app_number] => 09960509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507455 [patent_doc_number] => 06466510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-15 [patent_title] => '1-out-of-N decoder circuit' [patent_app_type] => B2 [patent_app_number] => 09/962410 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5306 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466510.pdf [firstpage_image] =>[orig_patent_app_number] => 09962410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1421320 [patent_doc_number] => 06509611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method for wrapped-gate MOSFET' [patent_app_type] => B1 [patent_app_number] => 09/961010 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 71 [patent_no_of_words] => 6582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509611.pdf [firstpage_image] =>[orig_patent_app_number] => 09961010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1384412 [patent_doc_number] => 06567321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Semiconductor memory device using dedicated command and address strobe signal and associated method' [patent_app_type] => B2 [patent_app_number] => 09/955420 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1761 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567321.pdf [firstpage_image] =>[orig_patent_app_number] => 09955420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5825939 [patent_doc_number] => 20020066948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Circuit board having interconnection ball lands and ball grid array (BGA) package using the circuit board' [patent_app_type] => new [patent_app_number] => 09/955245 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3255 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066948.pdf [firstpage_image] =>[orig_patent_app_number] => 09955245 [rel_patent_id] =>[rel_patent_doc_number] =>)