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Tu Tu V. Ho

Examiner (ID: 15910)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2804
Issued Applications
2592
Pending Applications
124
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6075892 [patent_doc_number] => 20020079497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Vertical cavity surface emitting laser with single mode confinement' [patent_app_type] => new [patent_app_number] => 09/954510 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3387 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079497.pdf [firstpage_image] =>[orig_patent_app_number] => 09954510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/954510
Vertical cavity surface emitting laser with single mode confinement Sep 16, 2001 Issued
Array ( [id] => 1396192 [patent_doc_number] => 06560146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Dynamic column block selection' [patent_app_type] => B2 [patent_app_number] => 09/956416 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5119 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560146.pdf [firstpage_image] =>[orig_patent_app_number] => 09956416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956416
Dynamic column block selection Sep 16, 2001 Issued
Array ( [id] => 1441054 [patent_doc_number] => 06495912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Structure of ceramic package with integrated passive devices' [patent_app_type] => B1 [patent_app_number] => 09/953610 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 5695 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495912.pdf [firstpage_image] =>[orig_patent_app_number] => 09953610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953610
Structure of ceramic package with integrated passive devices Sep 16, 2001 Issued
Array ( [id] => 1214153 [patent_doc_number] => 06710385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Semiconductor memory device using ferroelectric film' [patent_app_type] => B2 [patent_app_number] => 09/948877 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 9698 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/710/06710385.pdf [firstpage_image] =>[orig_patent_app_number] => 09948877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948877
Semiconductor memory device using ferroelectric film Sep 9, 2001 Issued
Array ( [id] => 1035119 [patent_doc_number] => 06876066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Packaged microelectronic devices and methods of forming same' [patent_app_type] => utility [patent_app_number] => 09/944246 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6451 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/876/06876066.pdf [firstpage_image] =>[orig_patent_app_number] => 09944246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944246
Packaged microelectronic devices and methods of forming same Aug 29, 2001 Issued
Array ( [id] => 6748007 [patent_doc_number] => 20030042527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Programmable array logic or memory devices with asymmetrical tunnel barriers' [patent_app_type] => new [patent_app_number] => 09/943134 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14513 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042527.pdf [firstpage_image] =>[orig_patent_app_number] => 09943134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943134
Programmable array logic or memory devices with asymmetrical tunnel barriers Aug 29, 2001 Issued
Array ( [id] => 6237505 [patent_doc_number] => 20020043693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Dense backplane cell for configurable logic' [patent_app_type] => new [patent_app_number] => 09/943210 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2884 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043693.pdf [firstpage_image] =>[orig_patent_app_number] => 09943210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943210
Dense backplane cell for configurable logic Aug 29, 2001 Issued
Array ( [id] => 6030748 [patent_doc_number] => 20020018373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Single electron resistor memory device and method' [patent_app_type] => new [patent_app_number] => 09/944258 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9067 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20020018373.pdf [firstpage_image] =>[orig_patent_app_number] => 09944258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944258
Single electron resistor memory device and method Aug 28, 2001 Issued
Array ( [id] => 6476835 [patent_doc_number] => 20020024135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/939746 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 17938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024135.pdf [firstpage_image] =>[orig_patent_app_number] => 09939746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939746
Power switching semiconductor device with suppressed oscillation Aug 27, 2001 Issued
Array ( [id] => 1293328 [patent_doc_number] => 06630703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Magnetoresistive memory cell configuration and method for its production' [patent_app_type] => B2 [patent_app_number] => 09/940011 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6694 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630703.pdf [firstpage_image] =>[orig_patent_app_number] => 09940011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940011
Magnetoresistive memory cell configuration and method for its production Aug 26, 2001 Issued
Array ( [id] => 6061933 [patent_doc_number] => 20020031005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 09/931915 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9131 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031005.pdf [firstpage_image] =>[orig_patent_app_number] => 09931915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931915
Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device. Aug 19, 2001 Issued
Array ( [id] => 1491865 [patent_doc_number] => 06417561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Keepers for MRAM electrodes' [patent_app_type] => B1 [patent_app_number] => 09/916884 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5880 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417561.pdf [firstpage_image] =>[orig_patent_app_number] => 09916884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916884
Keepers for MRAM electrodes Jul 26, 2001 Issued
Array ( [id] => 1318761 [patent_doc_number] => 06608323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'n-type thiophene semiconductors' [patent_app_type] => B2 [patent_app_number] => 09/915210 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6765 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/608/06608323.pdf [firstpage_image] =>[orig_patent_app_number] => 09915210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915210
n-type thiophene semiconductors Jul 23, 2001 Issued
Array ( [id] => 1420317 [patent_doc_number] => 06521911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'High dielectric constant metal silicates formed by controlled metal-surface reactions' [patent_app_type] => B2 [patent_app_number] => 09/908766 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5105 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521911.pdf [firstpage_image] =>[orig_patent_app_number] => 09908766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908766
High dielectric constant metal silicates formed by controlled metal-surface reactions Jul 18, 2001 Issued
Array ( [id] => 1396353 [patent_doc_number] => 06548893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Apparatus and method for hermetically sealing and EMI shielding integrated circuits for high speed electronic packages' [patent_app_type] => B1 [patent_app_number] => 09/898567 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1450 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548893.pdf [firstpage_image] =>[orig_patent_app_number] => 09898567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898567
Apparatus and method for hermetically sealing and EMI shielding integrated circuits for high speed electronic packages Jul 2, 2001 Issued
Array ( [id] => 1536431 [patent_doc_number] => 06489645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Integrated circuit device including a layered superlattice material with an interface buffer layer' [patent_app_type] => B1 [patent_app_number] => 09/898927 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8313 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489645.pdf [firstpage_image] =>[orig_patent_app_number] => 09898927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898927
Integrated circuit device including a layered superlattice material with an interface buffer layer Jul 2, 2001 Issued
Array ( [id] => 1576369 [patent_doc_number] => 06469368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method for producing a high-speed power diode with soft recovery, and a power diode produced using such a method' [patent_app_type] => B2 [patent_app_number] => 09/897027 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469368.pdf [firstpage_image] =>[orig_patent_app_number] => 09897027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897027
Method for producing a high-speed power diode with soft recovery, and a power diode produced using such a method Jul 2, 2001 Issued
Array ( [id] => 1600418 [patent_doc_number] => 06475885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Source/drain formation with sub-amorphizing implantation' [patent_app_type] => B1 [patent_app_number] => 09/896490 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3659 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475885.pdf [firstpage_image] =>[orig_patent_app_number] => 09896490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896490
Source/drain formation with sub-amorphizing implantation Jun 28, 2001 Issued
Array ( [id] => 1529519 [patent_doc_number] => 06479884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Interim oxidation of silsesquioxane dielectric for dual damascene process' [patent_app_type] => B2 [patent_app_number] => 09/893786 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3791 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479884.pdf [firstpage_image] =>[orig_patent_app_number] => 09893786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893786
Interim oxidation of silsesquioxane dielectric for dual damascene process Jun 28, 2001 Issued
Array ( [id] => 1401116 [patent_doc_number] => 06534338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method for molding semiconductor package having a ceramic substrate' [patent_app_type] => B1 [patent_app_number] => 09/895767 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 3860 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534338.pdf [firstpage_image] =>[orig_patent_app_number] => 09895767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895767
Method for molding semiconductor package having a ceramic substrate Jun 28, 2001 Issued
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