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Tu Tu V. Ho

Examiner (ID: 15910)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2804
Issued Applications
2592
Pending Applications
124
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6290324 [patent_doc_number] => 20020055203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/896810 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7460 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055203.pdf [firstpage_image] =>[orig_patent_app_number] => 09896810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896810
Semiconductor device having heat detecting element and insulating cavity and method of manufacturing the same Jun 28, 2001 Issued
Array ( [id] => 6883958 [patent_doc_number] => 20010038113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Process for manufacturing a crystal axis-aligned vertical side wall device' [patent_app_type] => new [patent_app_number] => 09/894427 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038113.pdf [firstpage_image] =>[orig_patent_app_number] => 09894427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894427
Process for manufacturing a crystal axis-aligned vertical side wall device Jun 27, 2001 Issued
Array ( [id] => 1590942 [patent_doc_number] => 06483193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Fabrication process for a semiconductor device with damascene interconnect lines of the same level separated by insulators with different dielectric constants' [patent_app_type] => B2 [patent_app_number] => 09/893926 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6702 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483193.pdf [firstpage_image] =>[orig_patent_app_number] => 09893926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893926
Fabrication process for a semiconductor device with damascene interconnect lines of the same level separated by insulators with different dielectric constants Jun 27, 2001 Issued
Array ( [id] => 6076098 [patent_doc_number] => 20020079593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Semiconductor package having heat sink attached to substrate' [patent_app_type] => new [patent_app_number] => 09/893110 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3904 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079593.pdf [firstpage_image] =>[orig_patent_app_number] => 09893110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893110
Semiconductor package having heat sink attached to substrate Jun 25, 2001 Issued
Array ( [id] => 1417611 [patent_doc_number] => 06528896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Scalable two transistor memory device' [patent_app_type] => B2 [patent_app_number] => 09/884911 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5983 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528896.pdf [firstpage_image] =>[orig_patent_app_number] => 09884911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884911
Scalable two transistor memory device Jun 20, 2001 Issued
Array ( [id] => 1478422 [patent_doc_number] => 06388911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Bank select structure layout of read only memory without the junction leakage' [patent_app_type] => B1 [patent_app_number] => 09/880908 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2317 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 642 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388911.pdf [firstpage_image] =>[orig_patent_app_number] => 09880908 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880908
Bank select structure layout of read only memory without the junction leakage Jun 14, 2001 Issued
Array ( [id] => 5803636 [patent_doc_number] => 20020010906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Circuit pattern design method,exposure method, charged-particle beam exposure system' [patent_app_type] => new [patent_app_number] => 09/878286 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6071 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010906.pdf [firstpage_image] =>[orig_patent_app_number] => 09878286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878286
Circuit pattern design method, exposure method, charged-particle beam exposure system Jun 11, 2001 Issued
Array ( [id] => 1408262 [patent_doc_number] => 06560768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Circuit pattern design method, circuit pattern design system, and recording medium' [patent_app_type] => B2 [patent_app_number] => 09/878250 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7026 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560768.pdf [firstpage_image] =>[orig_patent_app_number] => 09878250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878250
Circuit pattern design method, circuit pattern design system, and recording medium Jun 11, 2001 Issued
Array ( [id] => 1393011 [patent_doc_number] => 06541285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method of estimating lifetime of semiconductor device, and method of reliability simulation' [patent_app_type] => B2 [patent_app_number] => 09/878839 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9677 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541285.pdf [firstpage_image] =>[orig_patent_app_number] => 09878839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878839
Method of estimating lifetime of semiconductor device, and method of reliability simulation Jun 10, 2001 Issued
Array ( [id] => 1421114 [patent_doc_number] => 06509594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Semiconductor memory device having MFMIS transistor and increased data storage time' [patent_app_type] => B2 [patent_app_number] => 09/874319 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2558 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509594.pdf [firstpage_image] =>[orig_patent_app_number] => 09874319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874319
Semiconductor memory device having MFMIS transistor and increased data storage time Jun 5, 2001 Issued
Array ( [id] => 6895233 [patent_doc_number] => 20010026023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Vertically mountable and alignable semiconductor device, assembly, and methods' [patent_app_type] => new [patent_app_number] => 09/873869 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4845 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026023.pdf [firstpage_image] =>[orig_patent_app_number] => 09873869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873869
Vertically mountable and alignable semiconductor device, assembly, and methods Jun 3, 2001 Issued
Array ( [id] => 7076913 [patent_doc_number] => 20010040257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/875407 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7768 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040257.pdf [firstpage_image] =>[orig_patent_app_number] => 09875407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875407
Semiconductor device with channel having plural impurity regions Jun 3, 2001 Issued
Array ( [id] => 1521930 [patent_doc_number] => 06502231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Integrated circuit template cell system and method' [patent_app_type] => B1 [patent_app_number] => 09/871473 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3159 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502231.pdf [firstpage_image] =>[orig_patent_app_number] => 09871473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871473
Integrated circuit template cell system and method May 30, 2001 Issued
Array ( [id] => 1459846 [patent_doc_number] => 06426526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Single sided buried strap' [patent_app_type] => B1 [patent_app_number] => 09/870068 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 4018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426526.pdf [firstpage_image] =>[orig_patent_app_number] => 09870068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870068
Single sided buried strap May 29, 2001 Issued
Array ( [id] => 1457786 [patent_doc_number] => 06462989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Technique for locally reducing effects on an analog signal due to changes on a reference bus in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/870088 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4067 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462989.pdf [firstpage_image] =>[orig_patent_app_number] => 09870088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870088
Technique for locally reducing effects on an analog signal due to changes on a reference bus in an integrated circuit May 29, 2001 Issued
Array ( [id] => 1517330 [patent_doc_number] => 06500746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods' [patent_app_type] => B2 [patent_app_number] => 09/870146 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 11978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500746.pdf [firstpage_image] =>[orig_patent_app_number] => 09870146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870146
Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods May 29, 2001 Issued
Array ( [id] => 7647010 [patent_doc_number] => 06476508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Temperature control structure for integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/866976 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3482 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476508.pdf [firstpage_image] =>[orig_patent_app_number] => 09866976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866976
Temperature control structure for integrated circuit May 28, 2001 Issued
Array ( [id] => 1420377 [patent_doc_number] => 06512259 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Capacitor with high- dielectric or ferroelectric material based on the fin stack principle' [patent_app_type] => B1 [patent_app_number] => 09/863925 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 4665 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512259.pdf [firstpage_image] =>[orig_patent_app_number] => 09863925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863925
Capacitor with high- dielectric or ferroelectric material based on the fin stack principle May 22, 2001 Issued
Array ( [id] => 6107104 [patent_doc_number] => 20020171078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Metal-oxide electron tunneling device for solar energy conversion' [patent_app_type] => new [patent_app_number] => 09/860988 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6968 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171078.pdf [firstpage_image] =>[orig_patent_app_number] => 09860988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860988
Metal-oxide electron tunneling device for solar energy conversion May 20, 2001 Issued
Array ( [id] => 1581128 [patent_doc_number] => 06423609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Methods of forming capacitors on a wafer, photolithographic methods of forming capacitors on a wafer, and semiconductor wafer' [patent_app_type] => B1 [patent_app_number] => 09/861286 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4278 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423609.pdf [firstpage_image] =>[orig_patent_app_number] => 09861286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861286
Methods of forming capacitors on a wafer, photolithographic methods of forming capacitors on a wafer, and semiconductor wafer May 17, 2001 Issued
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