| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 1507388
[patent_doc_number] => 06466489
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Use of source/drain asymmetry MOSFET devices in dynamic and analog circuits'
[patent_app_type] => B1
[patent_app_number] => 09/861295
[patent_app_country] => US
[patent_app_date] => 2001-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 9030
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/466/06466489.pdf
[firstpage_image] =>[orig_patent_app_number] => 09861295
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/861295 | Use of source/drain asymmetry MOSFET devices in dynamic and analog circuits | May 17, 2001 | Issued |
Array
(
[id] => 1593998
[patent_doc_number] => 06483861
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-19
[patent_title] => 'Silicon thin film structure for optoelectronic devices and method for fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 09/860382
[patent_app_country] => US
[patent_app_date] => 2001-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2832
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/483/06483861.pdf
[firstpage_image] =>[orig_patent_app_number] => 09860382
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/860382 | Silicon thin film structure for optoelectronic devices and method for fabricating the same | May 17, 2001 | Issued |
Array
(
[id] => 6107204
[patent_doc_number] => 20020171139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'HIGH PERFORMANCE AIR COOLED HEAT SINKS USED IN HIGH DENSITY PACKAGING APPLICATIONS'
[patent_app_type] => new
[patent_app_number] => 09/860978
[patent_app_country] => US
[patent_app_date] => 2001-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3276
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20020171139.pdf
[firstpage_image] =>[orig_patent_app_number] => 09860978
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/860978 | High performance air cooled heat sinks used in high density packaging applications | May 17, 2001 | Issued |
Array
(
[id] => 1509501
[patent_doc_number] => 06441484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-08-27
[patent_title] => 'Semiconductor device having switching elements around a central control circuit'
[patent_app_type] => B2
[patent_app_number] => 09/859408
[patent_app_country] => US
[patent_app_date] => 2001-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11442
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/441/06441484.pdf
[firstpage_image] =>[orig_patent_app_number] => 09859408
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/859408 | Semiconductor device having switching elements around a central control circuit | May 17, 2001 | Issued |
Array
(
[id] => 1480725
[patent_doc_number] => 06452282
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Insulating adhesive tape for a semiconductor chip package having a copper lead frame'
[patent_app_type] => B1
[patent_app_number] => 09/858445
[patent_app_country] => US
[patent_app_date] => 2001-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2278
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/452/06452282.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858445
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858445 | Insulating adhesive tape for a semiconductor chip package having a copper lead frame | May 16, 2001 | Issued |
Array
(
[id] => 1509289
[patent_doc_number] => 06441421
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'High dielectric constant materials forming components of DRAM storage cells'
[patent_app_type] => B1
[patent_app_number] => 09/858485
[patent_app_country] => US
[patent_app_date] => 2001-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 3747
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/441/06441421.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858485
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858485 | High dielectric constant materials forming components of DRAM storage cells | May 16, 2001 | Issued |
Array
(
[id] => 1391949
[patent_doc_number] => 06552433
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Bond pads using mesh pattern via structures for protecting devices/circuits under I/O pads'
[patent_app_type] => B1
[patent_app_number] => 09/858529
[patent_app_country] => US
[patent_app_date] => 2001-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2288
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/552/06552433.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858529
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858529 | Bond pads using mesh pattern via structures for protecting devices/circuits under I/O pads | May 16, 2001 | Issued |
Array
(
[id] => 1520612
[patent_doc_number] => 06413793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method of forming protrusions on single crystal silicon structures built on silicon-on-insulator wafers'
[patent_app_type] => B1
[patent_app_number] => 09/858469
[patent_app_country] => US
[patent_app_date] => 2001-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2982
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/413/06413793.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858469
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858469 | Method of forming protrusions on single crystal silicon structures built on silicon-on-insulator wafers | May 16, 2001 | Issued |
Array
(
[id] => 1340770
[patent_doc_number] => 06593649
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Methods of IC rerouting option for multiple package system applications'
[patent_app_type] => B1
[patent_app_number] => 09/858528
[patent_app_country] => US
[patent_app_date] => 2001-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4955
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 374
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593649.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858528
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858528 | Methods of IC rerouting option for multiple package system applications | May 16, 2001 | Issued |
Array
(
[id] => 6897474
[patent_doc_number] => 20010045639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-29
[patent_title] => 'Power wiring structure and semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/855605
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3805
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20010045639.pdf
[firstpage_image] =>[orig_patent_app_number] => 09855605
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/855605 | Low inductance power wiring structure and semiconductor device | May 15, 2001 | Issued |
Array
(
[id] => 6076008
[patent_doc_number] => 20020079532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Semiconductor memory and method of producing the same'
[patent_app_type] => new
[patent_app_number] => 09/855536
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3932
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20020079532.pdf
[firstpage_image] =>[orig_patent_app_number] => 09855536
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/855536 | Method of fabricating a semiconductor device and the semiconductor device with a capacitor structure having increased capacitance | May 15, 2001 | Issued |
Array
(
[id] => 1570171
[patent_doc_number] => 06498055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-24
[patent_title] => 'Semiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing system'
[patent_app_type] => B2
[patent_app_number] => 09/855529
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 38
[patent_no_of_words] => 14743
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/498/06498055.pdf
[firstpage_image] =>[orig_patent_app_number] => 09855529
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/855529 | Semiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing system | May 15, 2001 | Issued |
Array
(
[id] => 1509484
[patent_doc_number] => 06441478
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-08-27
[patent_title] => 'Semiconductor package having metal-pattern bonding and method of fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 09/858408
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2322
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/441/06441478.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858408
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858408 | Semiconductor package having metal-pattern bonding and method of fabricating the same | May 15, 2001 | Issued |
Array
(
[id] => 1507264
[patent_doc_number] => 06440779
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Semiconductor package based on window pad type of leadframe and method of fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/859098
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2031
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/440/06440779.pdf
[firstpage_image] =>[orig_patent_app_number] => 09859098
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/859098 | Semiconductor package based on window pad type of leadframe and method of fabricating the same | May 15, 2001 | Issued |
Array
(
[id] => 6028633
[patent_doc_number] => 20020017644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-14
[patent_title] => 'Buried channel strained silicon FET using a supply layer created through ion implantation'
[patent_app_type] => new
[patent_app_number] => 09/859138
[patent_app_country] => US
[patent_app_date] => 2001-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4238
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20020017644.pdf
[firstpage_image] =>[orig_patent_app_number] => 09859138
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/859138 | Buried channel strained silicon FET using a supply layer created through ion implantation | May 15, 2001 | Issued |
Array
(
[id] => 6885901
[patent_doc_number] => 20010019170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-06
[patent_title] => 'Multichip module having a stacked chip arrangement'
[patent_app_type] => new
[patent_app_number] => 09/854486
[patent_app_country] => US
[patent_app_date] => 2001-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2319
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20010019170.pdf
[firstpage_image] =>[orig_patent_app_number] => 09854486
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/854486 | Multichip module having a stacked chip arrangement | May 14, 2001 | Issued |
Array
(
[id] => 1478066
[patent_doc_number] => 06451653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-09-17
[patent_title] => 'MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION'
[patent_app_type] => B2
[patent_app_number] => 09/858335
[patent_app_country] => US
[patent_app_date] => 2001-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 3655
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/451/06451653.pdf
[firstpage_image] =>[orig_patent_app_number] => 09858335
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/858335 | MANUFACTURING PROCESS FOR THE INTEGRATION IN A SEMICONDUCTOR CHIP OF AN INTEGRATED CIRCUIT INCLUDING A HIGH-DENSITY INTEGRATED CIRCUIT COMPONENTS PORTION AND A HIGH-PERFORMANCE LOGIC INTEGRATED CIRCUIT COMPONENTS PORTION | May 14, 2001 | Issued |
Array
(
[id] => 1452346
[patent_doc_number] => 06455931
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Monolithic microelectronic array structure having substrate islands and its fabrication'
[patent_app_type] => B1
[patent_app_number] => 09/859618
[patent_app_country] => US
[patent_app_date] => 2001-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 21
[patent_no_of_words] => 4552
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455931.pdf
[firstpage_image] =>[orig_patent_app_number] => 09859618
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/859618 | Monolithic microelectronic array structure having substrate islands and its fabrication | May 14, 2001 | Issued |
Array
(
[id] => 6879046
[patent_doc_number] => 20010030331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-18
[patent_title] => 'Semiconductor switching device and method of controlling a carrier lifetime in a semiconductor switching device'
[patent_app_type] => new
[patent_app_number] => 09/853775
[patent_app_country] => US
[patent_app_date] => 2001-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4150
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20010030331.pdf
[firstpage_image] =>[orig_patent_app_number] => 09853775
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/853775 | Semiconductor switching device and method of controlling a carrier lifetime in a semiconductor switching device | May 13, 2001 | Issued |
Array
(
[id] => 6891252
[patent_doc_number] => 20010017414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Flip chip with integrated mask and underfill'
[patent_app_type] => new
[patent_app_number] => 09/850808
[patent_app_country] => US
[patent_app_date] => 2001-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 5652
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20010017414.pdf
[firstpage_image] =>[orig_patent_app_number] => 09850808
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/850808 | Flip chip with integrated mask and underfill | May 7, 2001 | Abandoned |