
Tu Tu V Ho
Examiner (ID: 15910, Phone: (571)272-1778 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 2804 |
| Issued Applications | 2592 |
| Pending Applications | 124 |
| Abandoned Applications | 142 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20113263
[patent_doc_number] => 12364019
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/428844
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 6502
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428844
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428844 | Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same | Jan 30, 2024 | Issued |
Array
(
[id] => 19842798
[patent_doc_number] => 12255199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Multi-bit structure
[patent_app_type] => utility
[patent_app_number] => 18/415211
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 11766
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415211
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415211 | Multi-bit structure | Jan 16, 2024 | Issued |
Array
(
[id] => 20119568
[patent_doc_number] => 12369306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Memory cell and semiconductor memory device with the same
[patent_app_type] => utility
[patent_app_number] => 18/411032
[patent_app_country] => US
[patent_app_date] => 2024-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 23
[patent_no_of_words] => 2460
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411032
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/411032 | Memory cell and semiconductor memory device with the same | Jan 11, 2024 | Issued |
Array
(
[id] => 19654487
[patent_doc_number] => 12176287
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Integrated circuit devices having improved contact plug structures therein
[patent_app_type] => utility
[patent_app_number] => 18/409447
[patent_app_country] => US
[patent_app_date] => 2024-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 13502
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409447
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/409447 | Integrated circuit devices having improved contact plug structures therein | Jan 9, 2024 | Issued |
Array
(
[id] => 20245929
[patent_doc_number] => 12426274
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Method for MRAM top electrode connection
[patent_app_type] => utility
[patent_app_number] => 18/408892
[patent_app_country] => US
[patent_app_date] => 2024-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 4558
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408892
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/408892 | Method for MRAM top electrode connection | Jan 9, 2024 | Issued |
Array
(
[id] => 19146568
[patent_doc_number] => 20240145598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => DIELECTRIC ISOLATION LAYER BETWEEN A NANOWIRE TRANSISTOR AND A SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/404619
[patent_app_country] => US
[patent_app_date] => 2024-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11566
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404619
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/404619 | Dielectric isolation layer between a nanowire transistor and a substrate | Jan 3, 2024 | Issued |
Array
(
[id] => 19223585
[patent_doc_number] => 20240188289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
[patent_app_type] => utility
[patent_app_number] => 18/404204
[patent_app_country] => US
[patent_app_date] => 2024-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8361
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/404204 | Semiconductor device and method of manufacturing | Jan 3, 2024 | Issued |
Array
(
[id] => 20319194
[patent_doc_number] => 12457756
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => 3D printed semiconductor package
[patent_app_type] => utility
[patent_app_number] => 18/404496
[patent_app_country] => US
[patent_app_date] => 2024-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 1047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404496
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/404496 | 3D printed semiconductor package | Jan 3, 2024 | Issued |
Array
(
[id] => 19102740
[patent_doc_number] => 20240121968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => 3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH CONNECTIVITY STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/389769
[patent_app_country] => US
[patent_app_date] => 2023-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389769
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/389769 | 3D semiconductor device, structure and methods with connectivity structures | Dec 18, 2023 | Issued |
Array
(
[id] => 19261001
[patent_doc_number] => 12021067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-25
[patent_title] => 3D semiconductor device, structure and methods with connectivity structures
[patent_app_type] => utility
[patent_app_number] => 18/389752
[patent_app_country] => US
[patent_app_date] => 2023-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 76
[patent_no_of_words] => 25043
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389752
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/389752 | 3D semiconductor device, structure and methods with connectivity structures | Dec 18, 2023 | Issued |
Array
(
[id] => 19052609
[patent_doc_number] => 20240094578
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => LIQUID CRYSTAL DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/523145
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7513
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523145
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/523145 | Liquid crystal display device | Nov 28, 2023 | Issued |
Array
(
[id] => 19086296
[patent_doc_number] => 20240113097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => Integrated Standard Cell Structure
[patent_app_type] => utility
[patent_app_number] => 18/522727
[patent_app_country] => US
[patent_app_date] => 2023-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8523
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522727
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/522727 | Integrated standard cell structure | Nov 28, 2023 | Issued |
Array
(
[id] => 19057182
[patent_doc_number] => 20240099151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => SUB 60NM ETCHLESS MRAM DEVICES BY ION BEAM ETCHING FABRICATED T-SHAPED BOTTOM ELECTRODE
[patent_app_type] => utility
[patent_app_number] => 18/521560
[patent_app_country] => US
[patent_app_date] => 2023-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2144
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521560
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/521560 | Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode | Nov 27, 2023 | Issued |
Array
(
[id] => 19654537
[patent_doc_number] => 12176338
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Semiconductor device, method of and system for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/519486
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 17357
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519486
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/519486 | Semiconductor device, method of and system for manufacturing semiconductor device | Nov 26, 2023 | Issued |
Array
(
[id] => 20274899
[patent_doc_number] => 12444684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Semiconductor device including parallel configuration
[patent_app_type] => utility
[patent_app_number] => 18/519513
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 7053
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519513
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/519513 | Semiconductor device including parallel configuration | Nov 26, 2023 | Issued |
Array
(
[id] => 19945602
[patent_doc_number] => 12317754
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Magnetic tunnel junction structures and related methods
[patent_app_type] => utility
[patent_app_number] => 18/516751
[patent_app_country] => US
[patent_app_date] => 2023-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 1019
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516751
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/516751 | Magnetic tunnel junction structures and related methods | Nov 20, 2023 | Issued |
Array
(
[id] => 19040421
[patent_doc_number] => 20240090236
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => MULTI-LEVEL MAGNETIC TUNNEL JUNCTION NOR DEVICE WITH WRAP-AROUND GATE ELECTRODES AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/510808
[patent_app_country] => US
[patent_app_date] => 2023-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14283
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510808
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/510808 | Multi-level magnetic tunnel junction nor device with wrap-around gate electrodes and methods for forming the same | Nov 15, 2023 | Issued |
Array
(
[id] => 19937035
[patent_doc_number] => 12310257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Spacer scheme and method for MRAM
[patent_app_type] => utility
[patent_app_number] => 18/507152
[patent_app_country] => US
[patent_app_date] => 2023-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 25
[patent_no_of_words] => 3259
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507152
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/507152 | Spacer scheme and method for MRAM | Nov 12, 2023 | Issued |
Array
(
[id] => 19640467
[patent_doc_number] => 12171092
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-17
[patent_title] => Layout of static random access memory periphery circuit
[patent_app_type] => utility
[patent_app_number] => 18/506122
[patent_app_country] => US
[patent_app_date] => 2023-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 11494
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18506122
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/506122 | Layout of static random access memory periphery circuit | Nov 8, 2023 | Issued |
Array
(
[id] => 19918591
[patent_doc_number] => 12293967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-06
[patent_title] => Three-dimensional semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/505998
[patent_app_country] => US
[patent_app_date] => 2023-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 29
[patent_no_of_words] => 1190
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505998
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/505998 | Three-dimensional semiconductor device | Nov 8, 2023 | Issued |