Search

Tu Tu V. Ho

Examiner (ID: 2205, Phone: (571)272-1778 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2830
Issued Applications
2617
Pending Applications
120
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16812330 [patent_doc_number] => 20210134885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => THREE DIMENSIONAL MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/144669 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144669
Three dimensional memory array Jan 7, 2021 Issued
Array ( [id] => 17692529 [patent_doc_number] => 20220199822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/144175 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144175 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144175
Semiconductor device and method for manufacturing the same Jan 7, 2021 Issued
Array ( [id] => 17723420 [patent_doc_number] => 20220216142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => SEMICONDUCTOR MEMORY STRUCTURE AND INTERCONNECT STRUCTURE OF SEMICONDUCTOR MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/142158 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142158
Semiconductor memory structure and interconnect structure of semiconductor memory structure Jan 4, 2021 Issued
Array ( [id] => 19231190 [patent_doc_number] => 12010841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings [patent_app_type] => utility [patent_app_number] => 17/136471 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 50 [patent_no_of_words] => 19200 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136471
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings Dec 28, 2020 Issued
Array ( [id] => 18175184 [patent_doc_number] => 11574901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/135614 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 24298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135614
Semiconductor device and method for manufacturing the same Dec 27, 2020 Issued
Array ( [id] => 18001091 [patent_doc_number] => 11502202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Transistors with uniform source/drain epitaxy [patent_app_type] => utility [patent_app_number] => 17/133165 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133165
Transistors with uniform source/drain epitaxy Dec 22, 2020 Issued
Array ( [id] => 16827725 [patent_doc_number] => 20210143018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/129649 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129649
Semiconductor device and a method for fabricating the same Dec 20, 2020 Issued
Array ( [id] => 16765593 [patent_doc_number] => 20210111175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING VERTICAL ROUTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/129763 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129763
Semiconductor device including vertical routing structure and method for manufacturing the same Dec 20, 2020 Issued
Array ( [id] => 17825990 [patent_doc_number] => 11430947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Sub 60nm etchless MRAM devices by ion beam etching fabricated t-shaped bottom electrode [patent_app_type] => utility [patent_app_number] => 17/121394 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121394
Sub 60nm etchless MRAM devices by ion beam etching fabricated t-shaped bottom electrode Dec 13, 2020 Issued
Array ( [id] => 17676707 [patent_doc_number] => 20220189874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => NON-ORTHOGONAL SLOTTED VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/121645 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121645
Non-orthogonal slotted vias for semiconductor devices and associated systems and methods Dec 13, 2020 Issued
Array ( [id] => 16731475 [patent_doc_number] => 20210098623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ASYMMETRIC STRAINED SOURCE/DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/120243 [patent_app_country] => US [patent_app_date] => 2020-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120243
Method for fabricating semiconductor device with asymmetric strained source/drain structure Dec 12, 2020 Issued
Array ( [id] => 16904947 [patent_doc_number] => 20210183863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/118894 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118894
Memory device and method of manufacturing the same Dec 10, 2020 Issued
Array ( [id] => 16731474 [patent_doc_number] => 20210098622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ASYMMETRIC STRAINED SOURCE/DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/118524 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118524
Method for fabricating semiconductor device with asymmetric strained source/drain structure Dec 9, 2020 Issued
Array ( [id] => 16731470 [patent_doc_number] => 20210098618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Negative Capacitance Transistor with a Diffusion Blocking Layer [patent_app_type] => utility [patent_app_number] => 17/113821 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113821
Negative capacitance transistor with a diffusion blocking layer Dec 6, 2020 Issued
Array ( [id] => 16723757 [patent_doc_number] => 20210090904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => 3D PRINTED SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/114240 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114240
3D printed semiconductor package Dec 6, 2020 Issued
Array ( [id] => 17978822 [patent_doc_number] => 11495697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Optical component packaging structure [patent_app_type] => utility [patent_app_number] => 17/113349 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6431 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113349
Optical component packaging structure Dec 6, 2020 Issued
Array ( [id] => 18219678 [patent_doc_number] => 11594628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors [patent_app_type] => utility [patent_app_number] => 17/111561 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 9484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111561
Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors Dec 3, 2020 Issued
Array ( [id] => 19945473 [patent_doc_number] => 12317623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Imaging apparatus, manufacturing method thereof, and electronic equipment [patent_app_type] => utility [patent_app_number] => 17/756358 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 128 [patent_no_of_words] => 27476 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/756358
Imaging apparatus, manufacturing method thereof, and electronic equipment Nov 30, 2020 Issued
Array ( [id] => 17925958 [patent_doc_number] => 11469221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Integrated circuit and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/108635 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 14054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108635
Integrated circuit and manufacturing method thereof Nov 30, 2020 Issued
Array ( [id] => 18190620 [patent_doc_number] => 11581221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Method and IC design with non-linear power rails [patent_app_type] => utility [patent_app_number] => 17/106639 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 6555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106639
Method and IC design with non-linear power rails Nov 29, 2020 Issued
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