Search

Tu Tu V Ho

Examiner (ID: 12393, Phone: (571)272-1778 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2683
Issued Applications
2433
Pending Applications
108
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3813852 [patent_doc_number] => 05828902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Disc control device having reduced seek time by scheduling disc read requests' [patent_app_type] => 1 [patent_app_number] => 8/488868 [patent_app_country] => US [patent_app_date] => 1995-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7222 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828902.pdf [firstpage_image] =>[orig_patent_app_number] => 488868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488868
Disc control device having reduced seek time by scheduling disc read requests Jun 8, 1995 Issued
Array ( [id] => 3920037 [patent_doc_number] => 05752081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Signalling system and method for allowing a direct memory access (DMA) input/output (I/O) device on the peripheral component interconnect (PCI) bus to perform DMA transfers' [patent_app_type] => 1 [patent_app_number] => 8/488989 [patent_app_country] => US [patent_app_date] => 1995-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3815 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752081.pdf [firstpage_image] =>[orig_patent_app_number] => 488989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488989
Signalling system and method for allowing a direct memory access (DMA) input/output (I/O) device on the peripheral component interconnect (PCI) bus to perform DMA transfers Jun 7, 1995 Issued
Array ( [id] => 3878186 [patent_doc_number] => 05793979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'System for allocating the resources of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/476636 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 25393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793979.pdf [firstpage_image] =>[orig_patent_app_number] => 476636 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/476636
System for allocating the resources of a computer system Jun 6, 1995 Issued
Array ( [id] => 3795110 [patent_doc_number] => 05809329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System for managing the configuration of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/480764 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 25383 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809329.pdf [firstpage_image] =>[orig_patent_app_number] => 480764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/480764
System for managing the configuration of a computer system Jun 6, 1995 Issued
Array ( [id] => 3738856 [patent_doc_number] => 05652888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'System for interconnecting software components in an object oriented programming environment using a separate editor object for each run-time object instantiated for each selected component' [patent_app_type] => 1 [patent_app_number] => 8/486349 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5552 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652888.pdf [firstpage_image] =>[orig_patent_app_number] => 486349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486349
System for interconnecting software components in an object oriented programming environment using a separate editor object for each run-time object instantiated for each selected component Jun 6, 1995 Issued
Array ( [id] => 3635186 [patent_doc_number] => 05613070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'System for providing improved communication to data and computer communications network using parallel and serial communication buses and master and local routers' [patent_app_type] => 1 [patent_app_number] => 8/473612 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8874 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613070.pdf [firstpage_image] =>[orig_patent_app_number] => 473612 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/473612
System for providing improved communication to data and computer communications network using parallel and serial communication buses and master and local routers Jun 6, 1995 Issued
08/478500 METHOD AND SYSTEM FOR INTERCONNECTING SOFTWARE COMPONENTS Jun 6, 1995 Abandoned
Array ( [id] => 3660659 [patent_doc_number] => 05638515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Method for stripping dataframes from the communicating medium in an FDDI communications network' [patent_app_type] => 1 [patent_app_number] => 8/474992 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638515.pdf [firstpage_image] =>[orig_patent_app_number] => 474992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474992
Method for stripping dataframes from the communicating medium in an FDDI communications network Jun 6, 1995 Issued
Array ( [id] => 3797394 [patent_doc_number] => 05819107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method for managing the assignment of device drivers in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/480761 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 25422 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819107.pdf [firstpage_image] =>[orig_patent_app_number] => 480761 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/480761
Method for managing the assignment of device drivers in a computer system Jun 6, 1995 Issued
Array ( [id] => 3759627 [patent_doc_number] => 05754887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'System for limiting access of plurality of requests to peripheral bus by halting transmission to particular peripheral devices and resuming transmission after second predetermined time period expiration' [patent_app_type] => 1 [patent_app_number] => 8/472361 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754887.pdf [firstpage_image] =>[orig_patent_app_number] => 472361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472361
System for limiting access of plurality of requests to peripheral bus by halting transmission to particular peripheral devices and resuming transmission after second predetermined time period expiration Jun 6, 1995 Issued
Array ( [id] => 3802762 [patent_doc_number] => 05737547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device' [patent_app_type] => 1 [patent_app_number] => 8/480739 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 7491 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737547.pdf [firstpage_image] =>[orig_patent_app_number] => 480739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/480739
System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device Jun 6, 1995 Issued
Array ( [id] => 3812373 [patent_doc_number] => 05781796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'System for automatic configuration of I/O base address without configuration program using readout data on common bus by responding device' [patent_app_type] => 1 [patent_app_number] => 8/466997 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2203 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781796.pdf [firstpage_image] =>[orig_patent_app_number] => 466997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/466997
System for automatic configuration of I/O base address without configuration program using readout data on common bus by responding device Jun 5, 1995 Issued
Array ( [id] => 3984621 [patent_doc_number] => 05887194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked' [patent_app_type] => 1 [patent_app_number] => 8/472069 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10220 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887194.pdf [firstpage_image] =>[orig_patent_app_number] => 472069 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472069
Locking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains locked Jun 4, 1995 Issued
Array ( [id] => 3638080 [patent_doc_number] => 05608870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'System for combining a plurality of requests referencing a common target address into a single combined request having a single reference to the target address' [patent_app_type] => 1 [patent_app_number] => 8/459367 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8879 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608870.pdf [firstpage_image] =>[orig_patent_app_number] => 459367 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/459367
System for combining a plurality of requests referencing a common target address into a single combined request having a single reference to the target address Jun 1, 1995 Issued
Array ( [id] => 3899304 [patent_doc_number] => 05748984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Ad converting apparatus including holding means indicating whether or not data after AD conversion has been previously used' [patent_app_type] => 1 [patent_app_number] => 8/447588 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8065 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748984.pdf [firstpage_image] =>[orig_patent_app_number] => 447588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/447588
Ad converting apparatus including holding means indicating whether or not data after AD conversion has been previously used May 22, 1995 Issued
Array ( [id] => 3919958 [patent_doc_number] => 05752077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Data processing system having a multi-function input/output port with individual pull-up and pull-down control' [patent_app_type] => 1 [patent_app_number] => 8/440948 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4091 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752077.pdf [firstpage_image] =>[orig_patent_app_number] => 440948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440948
Data processing system having a multi-function input/output port with individual pull-up and pull-down control May 14, 1995 Issued
Array ( [id] => 3701576 [patent_doc_number] => 05664166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'System for generating a variable signal in response to a toggle signal selectively delayed using a clock edge and time delay measured from the clock edge' [patent_app_type] => 1 [patent_app_number] => 8/438882 [patent_app_country] => US [patent_app_date] => 1995-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6195 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664166.pdf [firstpage_image] =>[orig_patent_app_number] => 438882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438882
System for generating a variable signal in response to a toggle signal selectively delayed using a clock edge and time delay measured from the clock edge May 9, 1995 Issued
Array ( [id] => 3766724 [patent_doc_number] => 05721829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'System for automatic pause/resume of content delivered on a channel in response to switching to and from that channel and resuming so that a portion of the content is repeated' [patent_app_type] => 1 [patent_app_number] => 8/437087 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721829.pdf [firstpage_image] =>[orig_patent_app_number] => 437087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437087
System for automatic pause/resume of content delivered on a channel in response to switching to and from that channel and resuming so that a portion of the content is repeated May 4, 1995 Issued
Array ( [id] => 3936185 [patent_doc_number] => 05915131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method and apparatus for handling I/O requests utilizing separate programming interfaces to access separate I/O services' [patent_app_type] => 1 [patent_app_number] => 8/435677 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915131.pdf [firstpage_image] =>[orig_patent_app_number] => 435677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435677
Method and apparatus for handling I/O requests utilizing separate programming interfaces to access separate I/O services May 4, 1995 Issued
Array ( [id] => 3895225 [patent_doc_number] => 05799204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'System utilizing BIOS-compatible high performance video controller being default controller at boot-up and capable of switching to another graphics controller after boot-up' [patent_app_type] => 1 [patent_app_number] => 8/432106 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 9 [patent_no_of_words] => 5665 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799204.pdf [firstpage_image] =>[orig_patent_app_number] => 432106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/432106
System utilizing BIOS-compatible high performance video controller being default controller at boot-up and capable of switching to another graphics controller after boot-up Apr 30, 1995 Issued
Menu