Search

Tu Tu V. Ho

Examiner (ID: 5391, Phone: (571)272-1778 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2862
Issued Applications
2634
Pending Applications
132
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19639633 [patent_doc_number] => 12170248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Graphene BEOL integration interconnection structures [patent_app_type] => utility [patent_app_number] => 18/607380 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 7390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607380
Graphene BEOL integration interconnection structures Mar 14, 2024 Issued
Array ( [id] => 20260562 [patent_doc_number] => 12432933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor packages [patent_app_type] => utility [patent_app_number] => 18/596625 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596625
Semiconductor packages Mar 5, 2024 Issued
Array ( [id] => 19237455 [patent_doc_number] => 20240194650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MULTI-WAFER INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/587406 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587406
Multi-wafer integration Feb 25, 2024 Issued
Array ( [id] => 20793052 [patent_doc_number] => 12666986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Electronic package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/587276 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587276
Electronic package and manufacturing method thereof Feb 25, 2024 Issued
Array ( [id] => 20268687 [patent_doc_number] => 12439701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Power cell for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/586918 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586918
Power cell for semiconductor devices Feb 25, 2024 Issued
Array ( [id] => 20198483 [patent_doc_number] => 20250275193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => PUNCH THROUGH LEAKAGE CONTROL FOR SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/587430 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587430
PUNCH THROUGH LEAKAGE CONTROL FOR SEMICONDUCTOR STRUCTURES Feb 25, 2024 Pending
Array ( [id] => 19788559 [patent_doc_number] => 20250062238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR PACKAGE AND INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/587264 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587264
SEMICONDUCTOR PACKAGE AND INTEGRATED CIRCUIT DEVICE Feb 25, 2024 Pending
Array ( [id] => 19393343 [patent_doc_number] => 20240283213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR LASER DEVICE [patent_app_type] => utility [patent_app_number] => 18/438687 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438687
METHOD FOR MANUFACTURING SEMICONDUCTOR LASER DEVICE Feb 11, 2024 Pending
Array ( [id] => 19223584 [patent_doc_number] => 20240188288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING SUPPORT PILLARS [patent_app_type] => utility [patent_app_number] => 18/437665 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437665
Microelectronic devices and memory devices including support pillars Feb 8, 2024 Issued
Array ( [id] => 19515759 [patent_doc_number] => 20240347445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE INTERCONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/434474 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434474
INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE INTERCONNECTION STRUCTURE Feb 5, 2024 Pending
Array ( [id] => 20885980 [patent_doc_number] => 12702040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Low temperature substrate bonding method [patent_app_type] => utility [patent_app_number] => 18/433778 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433778
LOW TEMPERATURE SUBSTRATE BONDING METHOD Feb 5, 2024 Pending
Array ( [id] => 19906571 [patent_doc_number] => 12283590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Integrated circuit and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/432543 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 9338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432543
Integrated circuit and manufacturing method thereof Feb 4, 2024 Issued
Array ( [id] => 19912566 [patent_doc_number] => 12288785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Layout designs of integrated circuits having backside routing tracks [patent_app_type] => utility [patent_app_number] => 18/429926 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 54 [patent_no_of_words] => 13030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429926
Layout designs of integrated circuits having backside routing tracks Jan 31, 2024 Issued
Array ( [id] => 20698614 [patent_doc_number] => 20260130034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => DISPLAY MODULE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/687864 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18687864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/687864
DISPLAY MODULE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE THEREOF Jan 31, 2024 Pending
Array ( [id] => 20113263 [patent_doc_number] => 12364019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/428844 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428844
Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same Jan 30, 2024 Issued
Array ( [id] => 19484101 [patent_doc_number] => 20240332143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => HYBRID QUAD FLAT NO-LEADS (QFN) INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 18/429009 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429009
HYBRID QUAD FLAT NO-LEADS (QFN) INTEGRATED CIRCUIT PACKAGE Jan 30, 2024 Pending
Array ( [id] => 20916923 [patent_doc_number] => 12713792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 18/428896 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2299 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428896
DISPLAY DEVICE Jan 30, 2024 Pending
Array ( [id] => 20139512 [patent_doc_number] => 20250246556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => APPARATUSES FOR REDUCING PIN-TO-PIN INTERFERENCE IN PHYSICAL PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/428246 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428246
APPARATUSES FOR REDUCING PIN-TO-PIN INTERFERENCE IN PHYSICAL PROCESSORS Jan 30, 2024 Pending
Array ( [id] => 19452833 [patent_doc_number] => 20240312963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/417639 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417639 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417639
DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF Jan 18, 2024 Pending
Array ( [id] => 19842798 [patent_doc_number] => 12255199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Multi-bit structure [patent_app_type] => utility [patent_app_number] => 18/415211 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415211
Multi-bit structure Jan 16, 2024 Issued
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