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Tu Tu V Ho

Examiner (ID: 15910, Phone: (571)272-1778 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2804
Issued Applications
2592
Pending Applications
124
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13485539 [patent_doc_number] => 20180294312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => THREE DIMENSIONAL MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/482016 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482016
Three dimensional memory array Apr 6, 2017 Issued
Array ( [id] => 12498552 [patent_doc_number] => 09997478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-12 [patent_title] => Circuits and antennas integrated in dies and corresponding method [patent_app_type] => utility [patent_app_number] => 15/481910 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6867 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481910
Circuits and antennas integrated in dies and corresponding method Apr 6, 2017 Issued
Array ( [id] => 12215003 [patent_doc_number] => 09911819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Circuits using gate-all-around technology' [patent_app_type] => utility [patent_app_number] => 15/479803 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 47 [patent_no_of_words] => 12557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479803
Circuits using gate-all-around technology Apr 4, 2017 Issued
Array ( [id] => 12554202 [patent_doc_number] => 10014292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => 3D semiconductor device and structure [patent_app_type] => utility [patent_app_number] => 15/477106 [patent_app_country] => US [patent_app_date] => 2017-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 115 [patent_figures_cnt] => 141 [patent_no_of_words] => 64999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477106
3D semiconductor device and structure Apr 1, 2017 Issued
Array ( [id] => 12416778 [patent_doc_number] => 09972539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/475097 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3140 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475097
Method of fabricating semiconductor device Mar 29, 2017 Issued
Array ( [id] => 13159605 [patent_doc_number] => 10096537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Thermal management systems, methods for making, and methods for using [patent_app_type] => utility [patent_app_number] => 15/475074 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 79 [patent_no_of_words] => 35589 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475074
Thermal management systems, methods for making, and methods for using Mar 29, 2017 Issued
Array ( [id] => 14177943 [patent_doc_number] => 10262992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Three dimensional LVDMOS transistor structures [patent_app_type] => utility [patent_app_number] => 15/472585 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6472 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15472585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/472585
Three dimensional LVDMOS transistor structures Mar 28, 2017 Issued
Array ( [id] => 13995993 [patent_doc_number] => 20190067154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => POWER MODULE, POWER SEMICONDUCTOR DEVICE AND POWER MODULE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/070839 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070839
Power module, power semiconductor device and power module manufacturing method Mar 26, 2017 Issued
Array ( [id] => 13640777 [patent_doc_number] => 09847349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-19 [patent_title] => Biasing the substrate region of an MOS transistor [patent_app_type] => utility [patent_app_number] => 15/463493 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2435 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463493
Biasing the substrate region of an MOS transistor Mar 19, 2017 Issued
Array ( [id] => 13031031 [patent_doc_number] => 10038141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Fabrication of correlated electron material devices [patent_app_type] => utility [patent_app_number] => 15/463546 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 10193 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463546
Fabrication of correlated electron material devices Mar 19, 2017 Issued
Array ( [id] => 12263835 [patent_doc_number] => 20180083031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/463582 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463582
Semiconductor memory device and method for manufacturing same Mar 19, 2017 Issued
Array ( [id] => 12396270 [patent_doc_number] => 09966345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-08 [patent_title] => Protective barrier for integrated circuit packages housing a voltage regulator and a load [patent_app_type] => utility [patent_app_number] => 15/463627 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463627
Protective barrier for integrated circuit packages housing a voltage regulator and a load Mar 19, 2017 Issued
Array ( [id] => 12257086 [patent_doc_number] => 09929235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 15/463551 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 12525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463551
Semiconductor device and method for fabricating the same Mar 19, 2017 Issued
Array ( [id] => 12355341 [patent_doc_number] => 09953959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Metal protected fan-out cavity [patent_app_type] => utility [patent_app_number] => 15/463523 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 11006 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463523
Metal protected fan-out cavity Mar 19, 2017 Issued
Array ( [id] => 12436989 [patent_doc_number] => 09978847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit [patent_app_type] => utility [patent_app_number] => 15/454184 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2320 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454184
Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit Mar 8, 2017 Issued
Array ( [id] => 12154681 [patent_doc_number] => 20180025945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'PNP-TYPE BIPOLAR TRANSISTOR MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/450114 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3609 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450114
PNP-type bipolar transistor manufacturing method Mar 5, 2017 Issued
Array ( [id] => 12115067 [patent_doc_number] => 09871063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-16 [patent_title] => 'Display driver semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/450083 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450083
Display driver semiconductor device and manufacturing method thereof Mar 5, 2017 Issued
Array ( [id] => 14346293 [patent_doc_number] => 20190155119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/084260 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16084260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/084260
Semiconductor apparatus and method for manufacturing semiconductor apparatus Mar 2, 2017 Issued
Array ( [id] => 11694356 [patent_doc_number] => 20170170073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'Method and Structure to Fabricate Closely Packed Hybrid Nanowires at Scaled Pitch' [patent_app_type] => utility [patent_app_number] => 15/443527 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443527
Method and structure to fabricate closely packed hybrid nanowires at scaled pitch Feb 26, 2017 Issued
Array ( [id] => 11666322 [patent_doc_number] => 20170155041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'ARMATURE-CLAD MRAM DEVICE' [patent_app_type] => utility [patent_app_number] => 15/432409 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432409
Armature-clad MRAM device Feb 13, 2017 Issued
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