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Array ( [id] => 11398121 [patent_doc_number] => 20170018658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'SOLID-SOURCE DIFFUSED JUNCTION FOR FIN-BASED ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 15/121879 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7483 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15121879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10053615 [patent_doc_number] => 09093501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Interconnection wires of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/322330 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 6145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10916443 [patent_doc_number] => 20140319462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'BUFFER LAYER OMEGA GATE' [patent_app_type] => utility [patent_app_number] => 14/322017 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11765198 [patent_doc_number] => 09373649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Array substrate and method for manufacturing the same, and display device' [patent_app_type] => utility [patent_app_number] => 14/422342 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8637 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14422342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10010771 [patent_doc_number] => 09054302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same' [patent_app_type] => utility [patent_app_number] => 14/313690 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7739 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10787642 [patent_doc_number] => 20160133798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'OPTOELECTRONIC COMPONENT INCLUDING A CONVERSION ELEMENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT INCLUDING A CONVERSION ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/897343 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7020 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14897343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10106895 [patent_doc_number] => 09142678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Semiconductor device having fin structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/308378 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4517 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10916579 [patent_doc_number] => 20140319597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'Methods And Systems For Gate Dimension Control In Multi-Gate Structures For Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 14/302839 [patent_app_country] => US [patent_app_date] => 2014-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5803 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14302839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043572 [patent_doc_number] => 20160240528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'IGBT WITH BUILT-IN DIODE AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/901622 [patent_app_country] => US [patent_app_date] => 2014-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5191 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043652 [patent_doc_number] => 20160240608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'FIELD-STOP REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/901606 [patent_app_country] => US [patent_app_date] => 2014-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3983 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10993453 [patent_doc_number] => 20160190400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'LIGHT-EMITTING DEVICE PACKAGE, MANUFACTURING METHOD THEREOF, AND VEHICLE LAMP AND BACKLIGHT UNIT INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 14/891304 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11674 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14891304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11207945 [patent_doc_number] => 09437577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Package on package structure with pillar bump pins and related method thereof' [patent_app_type] => utility [patent_app_number] => 14/273553 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1532 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10439120 [patent_doc_number] => 20150324131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SYSTEM AND METHOD FOR MEMORY ALLOCATION IN A MULTICLASS MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/273751 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10111682 [patent_doc_number] => 09147100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Method for enhancing surface characteristics of a fingerprint sensor and structure made of the same' [patent_app_type] => utility [patent_app_number] => 14/273743 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2472 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10440575 [patent_doc_number] => 20150325587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => '3D STACKED IC DEVICE WITH STEPPED SUBSTACK INTERLAYER CONNECTORS' [patent_app_type] => utility [patent_app_number] => 14/273206 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8306 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10343562 [patent_doc_number] => 20150228567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/273306 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3183 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10112404 [patent_doc_number] => 09147824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Reactive contacts for 2D layered metal dichalcogenides' [patent_app_type] => utility [patent_app_number] => 14/272889 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10402788 [patent_doc_number] => 20150287797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'HIGH-VOLTAGE METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/273538 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4027 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10035323 [patent_doc_number] => 09076645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-07 [patent_title] => 'Method of fabricating an interlayer structure of increased elasticity modulus' [patent_app_type] => utility [patent_app_number] => 14/272554 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10112253 [patent_doc_number] => 09147672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Three-dimensional multiple chip packages including multiple chip stacks' [patent_app_type] => utility [patent_app_number] => 14/273171 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273171 [rel_patent_id] =>[rel_patent_doc_number] =>)