Search

Tu Tu V. Ho

Examiner (ID: 15910)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
2804
Issued Applications
2592
Pending Applications
124
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5175243 [patent_doc_number] => 20070176301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Structure and Method for Bond Pads of Copper-Metallized Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/733859 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2435 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176301.pdf [firstpage_image] =>[orig_patent_app_number] => 11733859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733859
Structure and method for bond pads of copper-metallized integrated circuits Apr 10, 2007 Issued
Array ( [id] => 5066673 [patent_doc_number] => 20070187774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure' [patent_app_type] => utility [patent_app_number] => 11/784637 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3575 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187774.pdf [firstpage_image] =>[orig_patent_app_number] => 11784637 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784637
Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure Apr 8, 2007 Abandoned
Array ( [id] => 5123520 [patent_doc_number] => 20070235790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Capacitor structure of semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/730810 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5132 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235790.pdf [firstpage_image] =>[orig_patent_app_number] => 11730810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730810
Capacitor structure of semiconductor device and method of fabricating the same Apr 3, 2007 Issued
Array ( [id] => 282110 [patent_doc_number] => 07554110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'MOS devices with partial stressor channel' [patent_app_type] => utility [patent_app_number] => 11/732380 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4105 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554110.pdf [firstpage_image] =>[orig_patent_app_number] => 11732380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732380
MOS devices with partial stressor channel Apr 2, 2007 Issued
Array ( [id] => 4715172 [patent_doc_number] => 20080237694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module' [patent_app_type] => utility [patent_app_number] => 11/728960 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6644 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237694.pdf [firstpage_image] =>[orig_patent_app_number] => 11728960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728960
Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module Mar 26, 2007 Abandoned
Array ( [id] => 4715216 [patent_doc_number] => 20080237738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell arrangement; memory module' [patent_app_type] => utility [patent_app_number] => 11/728970 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8105 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237738.pdf [firstpage_image] =>[orig_patent_app_number] => 11728970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728970
Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell arrangement; memory module Mar 26, 2007 Abandoned
Array ( [id] => 592413 [patent_doc_number] => 07435987 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Forming a type I heterostructure in a group IV semiconductor' [patent_app_type] => utility [patent_app_number] => 11/728890 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2173 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/435/07435987.pdf [firstpage_image] =>[orig_patent_app_number] => 11728890 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728890
Forming a type I heterostructure in a group IV semiconductor Mar 26, 2007 Issued
Array ( [id] => 5177575 [patent_doc_number] => 20070178635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators' [patent_app_type] => utility [patent_app_number] => 11/728671 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10768 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20070178635.pdf [firstpage_image] =>[orig_patent_app_number] => 11728671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728671
Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators Mar 26, 2007 Issued
Array ( [id] => 5159969 [patent_doc_number] => 20070173013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Semiconductor fabrication that includes surface tension control' [patent_app_type] => utility [patent_app_number] => 11/726522 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5961 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20070173013.pdf [firstpage_image] =>[orig_patent_app_number] => 11726522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726522
Semiconductor fabrication that includes surface tension control Mar 21, 2007 Abandoned
Array ( [id] => 4829111 [patent_doc_number] => 20080128692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Multi-purpose poly edge test structure' [patent_app_type] => utility [patent_app_number] => 11/728050 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2762 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128692.pdf [firstpage_image] =>[orig_patent_app_number] => 11728050 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728050
Multi-purpose poly edge test structure Mar 21, 2007 Issued
Array ( [id] => 5010693 [patent_doc_number] => 20070281172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Semiconductor on insulator structure made using radiation annealing' [patent_app_type] => utility [patent_app_number] => 11/726290 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9561 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281172.pdf [firstpage_image] =>[orig_patent_app_number] => 11726290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726290
Semiconductor on insulator structure made using radiation annealing Mar 20, 2007 Issued
Array ( [id] => 7597322 [patent_doc_number] => 07619255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Layer-stacked wiring and method for manufacturing same and semiconductor device using same and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/723600 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 10279 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619255.pdf [firstpage_image] =>[orig_patent_app_number] => 11723600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723600
Layer-stacked wiring and method for manufacturing same and semiconductor device using same and method for manufacturing semiconductor device Mar 20, 2007 Issued
Array ( [id] => 4737132 [patent_doc_number] => 20080230784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Cascode circuit employing a depletion-mode, GaN-based fet' [patent_app_type] => utility [patent_app_number] => 11/725760 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20080230784.pdf [firstpage_image] =>[orig_patent_app_number] => 11725760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725760
Cascode circuit employing a depletion-mode, GaN-based FET Mar 19, 2007 Issued
Array ( [id] => 5060399 [patent_doc_number] => 20070222036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Semiconductor memory device and methods of manufacturing and operating the same' [patent_app_type] => utility [patent_app_number] => 11/723490 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5906 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20070222036.pdf [firstpage_image] =>[orig_patent_app_number] => 11723490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723490
Semiconductor memory device and methods of manufacturing and operating the same Mar 19, 2007 Issued
Array ( [id] => 5088862 [patent_doc_number] => 20070228501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Magnetic recording element and magnetic memory' [patent_app_type] => utility [patent_app_number] => 11/725570 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15686 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228501.pdf [firstpage_image] =>[orig_patent_app_number] => 11725570 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725570
Magnetic recording element and magnetic memory Mar 19, 2007 Issued
Array ( [id] => 5163048 [patent_doc_number] => 20070284629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'High-performance field effect transistors with self-assembled nanodielectrics' [patent_app_type] => utility [patent_app_number] => 11/725350 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5995 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20070284629.pdf [firstpage_image] =>[orig_patent_app_number] => 11725350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725350
High-performance field effect transistors with self-assembled nanodielectrics Mar 18, 2007 Issued
Array ( [id] => 820874 [patent_doc_number] => 07408208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'III-nitride power semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/725430 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408208.pdf [firstpage_image] =>[orig_patent_app_number] => 11725430 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725430
III-nitride power semiconductor device Mar 18, 2007 Issued
Array ( [id] => 5163070 [patent_doc_number] => 20070284651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Charge-trap type non-volatile memory devices and related methods' [patent_app_type] => utility [patent_app_number] => 11/724870 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6649 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20070284651.pdf [firstpage_image] =>[orig_patent_app_number] => 11724870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724870
Charge-trap type non-volatile memory devices and related methods Mar 15, 2007 Issued
Array ( [id] => 4800434 [patent_doc_number] => 20080012021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Array substrate for display device' [patent_app_type] => utility [patent_app_number] => 11/724250 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3888 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20080012021.pdf [firstpage_image] =>[orig_patent_app_number] => 11724250 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724250
Array substrate for display device Mar 14, 2007 Issued
Array ( [id] => 5060313 [patent_doc_number] => 20070221950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Semiconductor device and a method for producing the same' [patent_app_type] => utility [patent_app_number] => 11/717790 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20070221950.pdf [firstpage_image] =>[orig_patent_app_number] => 11717790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717790
Semiconductor device and a method for producing the same Mar 13, 2007 Issued
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