Search

Tuan A. Hoang

Examiner (ID: 7516, Phone: (571)270-0406 , Office: P/2896 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2896, 2898
Total Applications
557
Issued Applications
368
Pending Applications
78
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19515952 [patent_doc_number] => 20240347638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => MULTI-FIN FIN-TYPE FIELD EFFECT TRANSISTOR WITH FINE-TUNED EFFECTIVE CHANNEL WIDTH [patent_app_type] => utility [patent_app_number] => 18/301382 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301382
MULTI-FIN FIN-TYPE FIELD EFFECT TRANSISTOR WITH FINE-TUNED EFFECTIVE CHANNEL WIDTH Apr 16, 2023 Pending
Array ( [id] => 18540923 [patent_doc_number] => 20230246034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => METAL OXIDE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/134117 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134117
Metal oxide and semiconductor device Apr 12, 2023 Issued
Array ( [id] => 18661385 [patent_doc_number] => 20230307399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/297807 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297807
Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices Apr 9, 2023 Pending
Array ( [id] => 18555461 [patent_doc_number] => 20230253478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => DIELECTRIC INNER SPACERS IN MULTI-GATE FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/297824 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297824
Dielectric inner spacers in multi-gate field-effect transistors Apr 9, 2023 Issued
Array ( [id] => 19484378 [patent_doc_number] => 20240332420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/192146 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192146
Semiconductor device and manufacturing method thereof Mar 28, 2023 Issued
Array ( [id] => 19086387 [patent_doc_number] => 20240113188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/190444 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190444
INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FABRICATING THE SAME Mar 26, 2023 Pending
Array ( [id] => 19468190 [patent_doc_number] => 20240321860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => ROW CELL CIRCUITS WITH ABRUPT DIFFUSION REGION WIDTH TRANSITIONS [patent_app_type] => utility [patent_app_number] => 18/189045 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189045
ROW CELL CIRCUITS WITH ABRUPT DIFFUSION REGION WIDTH TRANSITIONS Mar 22, 2023 Pending
Array ( [id] => 19055070 [patent_doc_number] => 20240097039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Crystallization of High-K Dielectric Layer [patent_app_type] => utility [patent_app_number] => 18/188314 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188314 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/188314
Crystallization of High-K Dielectric Layer Mar 21, 2023 Pending
Array ( [id] => 19161308 [patent_doc_number] => 20240154015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE WITH BACKSIDE INTERCONNECTION AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/187847 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18187847 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/187847
SEMICONDUCTOR DEVICE WITH BACKSIDE INTERCONNECTION AND METHOD FOR FORMING THE SAME Mar 21, 2023 Pending
Array ( [id] => 19071346 [patent_doc_number] => 20240105772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/188234 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188234 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/188234
INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF Mar 21, 2023 Pending
Array ( [id] => 20091052 [patent_doc_number] => 20250220988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/123653 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123653 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123653
Semiconductor devices Mar 19, 2023 Issued
Array ( [id] => 19468287 [patent_doc_number] => 20240321957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => FLEXIBLE SELF-ALIGNED POWER VIA SHAPE WITH GATE CUT FIRST [patent_app_type] => utility [patent_app_number] => 18/186227 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186227 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186227
FLEXIBLE SELF-ALIGNED POWER VIA SHAPE WITH GATE CUT FIRST Mar 19, 2023 Pending
Array ( [id] => 19452713 [patent_doc_number] => 20240312843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same [patent_app_type] => utility [patent_app_number] => 18/184024 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184024 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184024
Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same Mar 14, 2023 Pending
Array ( [id] => 19958506 [patent_doc_number] => 12328937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Integrated circuit devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/120547 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 3482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120547
Integrated circuit devices and methods of manufacturing the same Mar 12, 2023 Issued
Array ( [id] => 18906201 [patent_doc_number] => 20240021686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Source/Drain Contacts And Methods For Forming The Same [patent_app_type] => utility [patent_app_number] => 18/182144 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182144 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182144
Source/Drain Contacts And Methods For Forming The Same Mar 9, 2023 Pending
Array ( [id] => 19436002 [patent_doc_number] => 20240304500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => METHOD OF SELF-ALIGNED DIELECTRIC WALL FORMATION FOR FORKSHEET APPLICATION [patent_app_type] => utility [patent_app_number] => 18/178665 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178665
METHOD OF SELF-ALIGNED DIELECTRIC WALL FORMATION FOR FORKSHEET APPLICATION Mar 5, 2023 Pending
Array ( [id] => 18849094 [patent_doc_number] => 20230411498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/175821 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175821
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Feb 27, 2023 Pending
Array ( [id] => 19407274 [patent_doc_number] => 20240290785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => Reducing Defects In a Polysilicon Overlaid Fin Structure [patent_app_type] => utility [patent_app_number] => 18/176430 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176430
Reducing Defects In a Polysilicon Overlaid Fin Structure Feb 27, 2023 Pending
Array ( [id] => 19038474 [patent_doc_number] => 20240088289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => LOW-FREQUENCY NOSIE TRANSISTORS WITH CURVED CHANNELS [patent_app_type] => utility [patent_app_number] => 18/171362 [patent_app_country] => US [patent_app_date] => 2023-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171362 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171362
LOW-FREQUENCY NOSIE TRANSISTORS WITH CURVED CHANNELS Feb 18, 2023 Pending
Array ( [id] => 20457446 [patent_doc_number] => 12520518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Semiconductor device structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/109205 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 46 [patent_no_of_words] => 3233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109205
Semiconductor device structure and methods of forming the same Feb 12, 2023 Issued
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