Search

Tuan A. Hoang

Examiner (ID: 1082, Phone: (571)270-0406 , Office: P/2896 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2896, 2822
Total Applications
587
Issued Applications
385
Pending Applications
83
Abandoned Applications
132

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18812783 [patent_doc_number] => 20230387120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/229682 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229682
Semiconductor device structure and methods of forming the same Aug 2, 2023 Issued
Array ( [id] => 20509043 [patent_doc_number] => 12543335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Multilayer masking layer and method of forming same [patent_app_type] => utility [patent_app_number] => 18/364352 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 89 [patent_figures_cnt] => 91 [patent_no_of_words] => 11056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364352 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364352
Multilayer masking layer and method of forming same Aug 1, 2023 Issued
Array ( [id] => 18789629 [patent_doc_number] => 20230378329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => CONTROLLED DOPING IN A GATE DIELECTRIC LAYER [patent_app_type] => utility [patent_app_number] => 18/362266 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362266
CONTROLLED DOPING IN A GATE DIELECTRIC LAYER Jul 30, 2023 Pending
Array ( [id] => 18789416 [patent_doc_number] => 20230378078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => PACKAGE WITH FAN-OUT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/360656 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360656
PACKAGE WITH FAN-OUT STRUCTURES Jul 26, 2023 Pending
Array ( [id] => 18774635 [patent_doc_number] => 20230369466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/357795 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357795
Method for forming semiconductor device Jul 23, 2023 Issued
Array ( [id] => 20443085 [patent_doc_number] => 12513931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Multi-gate device and related methods [patent_app_type] => utility [patent_app_number] => 18/357464 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 4549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357464
Multi-gate device and related methods Jul 23, 2023 Issued
Array ( [id] => 19728675 [patent_doc_number] => 20250031426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => GATE HEIGHT OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/353691 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353691 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353691
GATE HEIGHT OPTIMIZATION Jul 16, 2023 Pending
Array ( [id] => 18757722 [patent_doc_number] => 20230361185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => ETCH PROFILE CONTROL OF VIA OPENING [patent_app_type] => utility [patent_app_number] => 18/352640 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352640
ETCH PROFILE CONTROL OF VIA OPENING Jul 13, 2023 Pending
Array ( [id] => 19712798 [patent_doc_number] => 20250022940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SEMICONDUCTOR DEVICES WITH IMPROVED GATE CONTROL [patent_app_type] => utility [patent_app_number] => 18/350429 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350429 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350429
SEMICONDUCTOR DEVICES WITH IMPROVED GATE CONTROL Jul 10, 2023 Pending
Array ( [id] => 20566017 [patent_doc_number] => 12568641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Semiconductor device with varying numbers of channel layers and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 18/349617 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 124 [patent_no_of_words] => 7670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349617
Semiconductor device with varying numbers of channel layers and method of fabrication thereof Jul 9, 2023 Issued
Array ( [id] => 18743494 [patent_doc_number] => 20230352482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/348818 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348818
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME Jul 6, 2023 Issued
Array ( [id] => 19531838 [patent_doc_number] => 20240355740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => Barrier Free Tungsten Liner in Contact Plugs and The Method Forming the Same [patent_app_type] => utility [patent_app_number] => 18/345303 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345303 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345303
Barrier Free Tungsten Liner in Contact Plugs and The Method Forming the Same Jun 29, 2023 Pending
Array ( [id] => 18743356 [patent_doc_number] => 20230352344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 18/344441 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344441
Semiconductor device and method Jun 28, 2023 Issued
Array ( [id] => 18865953 [patent_doc_number] => 20230420390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => LEADFRAME WITH PAD ANCHORING MEMBERS AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/339615 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339615
LEADFRAME WITH PAD ANCHORING MEMBERS AND METHOD OF FORMING THE SAME Jun 21, 2023 Pending
Array ( [id] => 19589682 [patent_doc_number] => 20240387239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/209488 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209488
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE Jun 13, 2023 Pending
Array ( [id] => 21014564 [patent_doc_number] => 12751062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-29 [patent_title] => Etch profile control of gate contact opening [patent_app_type] => utility [patent_app_number] => 18/329472 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 10567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329472
ETCH PROFILE CONTROL OF GATE CONTACT OPENING Jun 4, 2023 Pending
Array ( [id] => 19619209 [patent_doc_number] => 20240404889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 18/327491 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327491
SEMICONDUCTOR DEVICE AND METHODS OF FORMATION May 31, 2023 Pending
Array ( [id] => 21014532 [patent_doc_number] => 12751030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-29 [patent_title] => Semiconductor structure and forming method thereof [patent_app_type] => utility [patent_app_number] => 18/198338 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 33 [patent_no_of_words] => 6751 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/198338
SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF May 16, 2023 Pending
Array ( [id] => 19335656 [patent_doc_number] => 20240250086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => P-DIPOLE MATERIAL FOR STACKED TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/316146 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/316146
P-DIPOLE MATERIAL FOR STACKED TRANSISTORS May 10, 2023 Pending
Array ( [id] => 19335513 [patent_doc_number] => 20240249943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => N-DIPOLE MATERIAL FOR STACKED TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/315232 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315232
N-DIPOLE MATERIAL FOR STACKED TRANSISTORS May 9, 2023 Pending
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