Search

Tuan A. Hoang

Examiner (ID: 7516, Phone: (571)270-0406 , Office: P/2896 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2896, 2898
Total Applications
557
Issued Applications
368
Pending Applications
78
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20245965 [patent_doc_number] => 12426310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Gate-all-around devices with optimized gate spacers and gate end dielectric [patent_app_type] => utility [patent_app_number] => 18/168294 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 58 [patent_no_of_words] => 7298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168294
Gate-all-around devices with optimized gate spacers and gate end dielectric Feb 12, 2023 Issued
Array ( [id] => 18442312 [patent_doc_number] => 20230189608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/167523 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167523
DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME Feb 9, 2023 Pending
Array ( [id] => 19071423 [patent_doc_number] => 20240105849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/167423 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167423
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Feb 9, 2023 Pending
Array ( [id] => 19071095 [patent_doc_number] => 20240105521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH ISOLATION LAYER AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/166932 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166932
SEMICONDUCTOR DEVICE STRUCTURE WITH ISOLATION LAYER AND METHOD FOR FORMING THE SAME Feb 8, 2023 Pending
Array ( [id] => 19101106 [patent_doc_number] => 20240120334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH GATE DIELECTRIC LAYER AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/166750 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166750
SEMICONDUCTOR DEVICE STRUCTURE WITH GATE DIELECTRIC LAYER AND METHOD FOR FORMING THE SAME Feb 8, 2023 Pending
Array ( [id] => 18959012 [patent_doc_number] => 20240047339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/106540 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/106540
INTEGRATED CIRCUIT DEVICE Feb 6, 2023 Pending
Array ( [id] => 19349430 [patent_doc_number] => 20240258394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/162350 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162350 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162350
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Jan 30, 2023 Issued
Array ( [id] => 20245970 [patent_doc_number] => 12426315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => IC device with vertically-graded silicon germanium region adjacent device channel and method for forming [patent_app_type] => utility [patent_app_number] => 18/161219 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/161219
IC device with vertically-graded silicon germanium region adjacent device channel and method for forming Jan 29, 2023 Issued
Array ( [id] => 18424091 [patent_doc_number] => 20230178555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/102928 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102928
Semiconductor device structure and methods of forming the same Jan 29, 2023 Issued
Array ( [id] => 18442224 [patent_doc_number] => 20230189520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 18/103265 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 489 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103265
SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAME Jan 29, 2023 Pending
Array ( [id] => 18379832 [patent_doc_number] => 20230154921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => AIR SPACER AND CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/158036 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158036 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158036
Air spacer and capping structures in semiconductor devices Jan 22, 2023 Issued
Array ( [id] => 19335723 [patent_doc_number] => 20240250153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/099405 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099405
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Jan 19, 2023 Pending
Array ( [id] => 18833928 [patent_doc_number] => 20230402455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/097255 [patent_app_country] => US [patent_app_date] => 2023-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097255
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Jan 14, 2023 Pending
Array ( [id] => 19071092 [patent_doc_number] => 20240105518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/153304 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153304 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153304
METHOD FOR FORMING SEMICONDUCTOR DEVICE Jan 10, 2023 Pending
Array ( [id] => 19055024 [patent_doc_number] => 20240096993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => TRANSISTOR AND SEMICONDUCTOR DEVICE WITH MULTIPLE THRESHOLD VOLTAGES AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/151481 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151481
Transistor and semiconductor device with multiple threshold voltages and fabrication method thereof Jan 8, 2023 Issued
Array ( [id] => 18394966 [patent_doc_number] => 20230163187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => METAL GATE STRUCTURES FOR FIELD EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/151575 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151575
Metal gate structures for field effect transistors Jan 8, 2023 Issued
Array ( [id] => 19086386 [patent_doc_number] => 20240113187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => COMPOSITE GATE DIELECTRIC FOR HIGH-VOLTAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/150266 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150266
COMPOSITE GATE DIELECTRIC FOR HIGH-VOLTAGE DEVICE Jan 4, 2023 Pending
Array ( [id] => 19285898 [patent_doc_number] => 20240222375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => HYBRID CMOS WITH FIN AND NANOSHEET ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/089634 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089634
HYBRID CMOS WITH FIN AND NANOSHEET ARCHITECTURES Dec 27, 2022 Pending
Array ( [id] => 18789570 [patent_doc_number] => 20230378263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/085886 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085886
SEMICONDUCTOR DEVICE Dec 20, 2022 Pending
Array ( [id] => 18320572 [patent_doc_number] => 20230118700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => Inner Spacer Formation in Multi-Gate Transistors [patent_app_type] => utility [patent_app_number] => 18/066354 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066354
Inner spacer formation in multi-gate transistors Dec 14, 2022 Issued
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